{"id":"https://openalex.org/W4417169324","doi":"https://doi.org/10.1109/icecs66544.2025.11270557","title":"Design of a Retentive and Single-Event Upset Tolerant TSPC Flip-Flop","display_name":"Design of a Retentive and Single-Event Upset Tolerant TSPC Flip-Flop","publication_year":2025,"publication_date":"2025-11-17","ids":{"openalex":"https://openalex.org/W4417169324","doi":"https://doi.org/10.1109/icecs66544.2025.11270557"},"language":null,"primary_location":{"id":"doi:10.1109/icecs66544.2025.11270557","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecs66544.2025.11270557","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 32nd IEEE International Conference on Electronics, Circuits and Systems (ICECS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5107287883","display_name":"Ahmet Cirakoglu","orcid":"https://orcid.org/0009-0007-8152-5069"},"institutions":[{"id":"https://openalex.org/I98677209","display_name":"University of Edinburgh","ror":"https://ror.org/01nrxwf90","country_code":"GB","type":"education","lineage":["https://openalex.org/I98677209"]}],"countries":["GB"],"is_corresponding":true,"raw_author_name":"Ahmet Cirakoglu","raw_affiliation_strings":["University of Edinburgh,Centre for Electronics Frontiers, Institute for Integrated Micro and Nano Systems, School of Engineering,Edinburgh,United Kingdom"],"affiliations":[{"raw_affiliation_string":"University of Edinburgh,Centre for Electronics Frontiers, Institute for Integrated Micro and Nano Systems, School of Engineering,Edinburgh,United Kingdom","institution_ids":["https://openalex.org/I98677209"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5017301291","display_name":"Alexander Serb","orcid":"https://orcid.org/0000-0002-8034-2398"},"institutions":[{"id":"https://openalex.org/I98677209","display_name":"University of Edinburgh","ror":"https://ror.org/01nrxwf90","country_code":"GB","type":"education","lineage":["https://openalex.org/I98677209"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Alex Serb","raw_affiliation_strings":["University of Edinburgh,Centre for Electronics Frontiers, Institute for Integrated Micro and Nano Systems, School of Engineering,Edinburgh,United Kingdom"],"affiliations":[{"raw_affiliation_string":"University of Edinburgh,Centre for Electronics Frontiers, Institute for Integrated Micro and Nano Systems, School of Engineering,Edinburgh,United Kingdom","institution_ids":["https://openalex.org/I98677209"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5069930060","display_name":"Khaled Humood","orcid":"https://orcid.org/0000-0002-5275-6593"},"institutions":[{"id":"https://openalex.org/I98677209","display_name":"University of Edinburgh","ror":"https://ror.org/01nrxwf90","country_code":"GB","type":"education","lineage":["https://openalex.org/I98677209"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Khaled Humood","raw_affiliation_strings":["University of Edinburgh,Centre for Electronics Frontiers, Institute for Integrated Micro and Nano Systems, School of Engineering,Edinburgh,United Kingdom"],"affiliations":[{"raw_affiliation_string":"University of Edinburgh,Centre for Electronics Frontiers, Institute for Integrated Micro and Nano Systems, School of Engineering,Edinburgh,United Kingdom","institution_ids":["https://openalex.org/I98677209"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5077466475","display_name":"Mark Zwoli\u0144ski","orcid":"https://orcid.org/0000-0002-2230-625X"},"institutions":[{"id":"https://openalex.org/I43439940","display_name":"University of Southampton","ror":"https://ror.org/01ryk1543","country_code":"GB","type":"education","lineage":["https://openalex.org/I43439940"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Mark Zwolinski","raw_affiliation_strings":["University of Southampton,School of Electronics and Computer Science,Southampton,UK,SO17 1BJ"],"affiliations":[{"raw_affiliation_string":"University of Southampton,School of Electronics and Computer Science,Southampton,UK,SO17 1BJ","institution_ids":["https://openalex.org/I43439940"]}]},{"author_position":"last","author":{"id":null,"display_name":"Themis Prodromakis","orcid":null},"institutions":[{"id":"https://openalex.org/I98677209","display_name":"University of Edinburgh","ror":"https://ror.org/01nrxwf90","country_code":"GB","type":"education","lineage":["https://openalex.org/I98677209"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Themis Prodromakis","raw_affiliation_strings":["University of Edinburgh,Centre for Electronics Frontiers, Institute for Integrated Micro and Nano Systems, School of Engineering,Edinburgh,United Kingdom"],"affiliations":[{"raw_affiliation_string":"University of Edinburgh,Centre for Electronics Frontiers, Institute for Integrated Micro and Nano Systems, School of Engineering,Edinburgh,United Kingdom","institution_ids":["https://openalex.org/I98677209"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5107287883"],"corresponding_institution_ids":["https://openalex.org/I98677209"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.38700018,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"5"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9908999800682068,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9908999800682068,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.003700000001117587,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.0008999999845400453,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/upset","display_name":"Upset","score":0.7228999733924866},{"id":"https://openalex.org/keywords/data-retention","display_name":"Data retention","score":0.6064000129699707},{"id":"https://openalex.org/keywords/modular-design","display_name":"Modular design","score":0.49459999799728394},{"id":"https://openalex.org/keywords/monte-carlo-method","display_name":"Monte Carlo method","score":0.45399999618530273},{"id":"https://openalex.org/keywords/rendering","display_name":"Rendering (computer graphics)","score":0.388700008392334},{"id":"https://openalex.org/keywords/single-event-upset","display_name":"Single event upset","score":0.3393000066280365},{"id":"https://openalex.org/keywords/artificial-neural-network","display_name":"Artificial neural network","score":0.3244999945163727},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.32409998774528503}],"concepts":[{"id":"https://openalex.org/C2778002589","wikidata":"https://www.wikidata.org/wiki/Q2406791","display_name":"Upset","level":2,"score":0.7228999733924866},{"id":"https://openalex.org/C2780866740","wikidata":"https://www.wikidata.org/wiki/Q5227345","display_name":"Data retention","level":2,"score":0.6064000129699707},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5562000274658203},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5067999958992004},{"id":"https://openalex.org/C101468663","wikidata":"https://www.wikidata.org/wiki/Q1620158","display_name":"Modular design","level":2,"score":0.49459999799728394},{"id":"https://openalex.org/C19499675","wikidata":"https://www.wikidata.org/wiki/Q232207","display_name":"Monte Carlo method","level":2,"score":0.45399999618530273},{"id":"https://openalex.org/C205711294","wikidata":"https://www.wikidata.org/wiki/Q176953","display_name":"Rendering (computer graphics)","level":2,"score":0.388700008392334},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.35530000925064087},{"id":"https://openalex.org/C2780073065","wikidata":"https://www.wikidata.org/wiki/Q1476733","display_name":"Single event upset","level":3,"score":0.3393000066280365},{"id":"https://openalex.org/C50644808","wikidata":"https://www.wikidata.org/wiki/Q192776","display_name":"Artificial neural network","level":2,"score":0.3244999945163727},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.32409998774528503},{"id":"https://openalex.org/C2780080018","wikidata":"https://www.wikidata.org/wiki/Q2439233","display_name":"Tolerance analysis","level":2,"score":0.3197000026702881},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3107999861240387},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.30709999799728394},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.30090001225471497},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.2924000024795532},{"id":"https://openalex.org/C2778309119","wikidata":"https://www.wikidata.org/wiki/Q5121614","display_name":"Circuit reliability","level":4,"score":0.29170000553131104},{"id":"https://openalex.org/C104267543","wikidata":"https://www.wikidata.org/wiki/Q208163","display_name":"Signal processing","level":3,"score":0.2903999984264374},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2680000066757202},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.2669999897480011},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.2590000033378601},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.25859999656677246},{"id":"https://openalex.org/C193519340","wikidata":"https://www.wikidata.org/wiki/Q891179","display_name":"Data loss","level":2,"score":0.25130000710487366}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/icecs66544.2025.11270557","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecs66544.2025.11270557","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 32nd IEEE International Conference on Electronics, Circuits and Systems (ICECS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320334627","display_name":"Engineering and Physical Sciences Research Council","ror":"https://ror.org/0439y7842"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":20,"referenced_works":["https://openalex.org/W71096308","https://openalex.org/W1995665089","https://openalex.org/W1998973216","https://openalex.org/W2016016211","https://openalex.org/W2132729131","https://openalex.org/W2778408213","https://openalex.org/W2943419595","https://openalex.org/W2945143322","https://openalex.org/W2980855339","https://openalex.org/W3092381027","https://openalex.org/W3113229535","https://openalex.org/W3135298190","https://openalex.org/W3159567999","https://openalex.org/W3159800694","https://openalex.org/W4226395151","https://openalex.org/W4379984329","https://openalex.org/W4402572261","https://openalex.org/W4402669255","https://openalex.org/W4409975470","https://openalex.org/W4411173518"],"related_works":[],"abstract_inverted_index":{"True":[0],"single-phase-clock":[1],"flip-flops":[2],"(TSPC-FFs)":[3],"offer":[4],"a":[5,53,65,80,91,136],"power-":[6],"and":[7,21,107,117],"area-efficient":[8],"alternative":[9],"to":[10,135],"conventional":[11],"master\u2013slave":[12],"(MS)":[13],"flip-flops,":[14],"making":[15],"them":[16],"well":[17],"suited":[18],"for":[19,30,68,101],"high-speed":[20],"low-power":[22],"digital":[23],"designs.":[24],"For":[25],"instance,":[26],"TSPC-FFs":[27],"are":[28],"suitable":[29],"improving":[31],"the":[32,47,62,123],"performance":[33],"of":[34,43,49,56,64],"novel":[35],"deep":[36],"neural":[37],"network":[38],"hardware":[39],"accelerators.":[40],"The":[41],"benefits":[42],"TSPC-FF":[44,57,86],"also":[45],"meet":[46],"needs":[48],"space":[50],"applications.":[51],"However,":[52],"major":[54],"disadvantage":[55],"is":[58],"data":[59,108],"loss":[60],"during":[61,110],"absence":[63],"clock":[66],"signal":[67],"an":[69,127],"extended":[70],"period,":[71],"rendering":[72],"energy-efficient":[73],"schemes":[74],"like":[75],"clock-gating":[76],"unfeasible.":[77],"We":[78],"propose":[79],"new":[81],"single-event":[82],"upset":[83],"(SEU)":[84],"tolerant":[85],"design":[87,125],"that":[88,97,122],"uniquely":[89],"incorporates":[90],"hardened":[92],"dual-inverter":[93],"latch":[94],"using":[95],"C-elements":[96],"can":[98],"be":[99],"used":[100],"soft-error":[102],"mitigation":[103],"in":[104],"normal":[105],"operation":[106],"retention":[109],"clock-gating.":[111],"Post-layout":[112],"simulations":[113],"across":[114],"process-voltage-temperature":[115],"corners":[116],"Monte":[118],"Carlo":[119],"variations":[120],"show":[121],"proposed":[124],"achieves":[126],"approximately":[128],"4.5\u00d7":[129],"higher":[130],"minimum":[131],"critical":[132],"charge":[133],"compared":[134],"recent":[137],"rad-hard":[138],"reference":[139],"design,":[140],"which":[141],"uses":[142],"dual":[143],"modular":[144],"redundancy.":[145]},"counts_by_year":[],"updated_date":"2026-04-09T08:11:56.329763","created_date":"2025-12-09T00:00:00"}
