{"id":"https://openalex.org/W4389529169","doi":"https://doi.org/10.1109/icecs58634.2023.10382949","title":"A Generic CDC Modeling for Data Stability Verification","display_name":"A Generic CDC Modeling for Data Stability Verification","publication_year":2023,"publication_date":"2023-12-04","ids":{"openalex":"https://openalex.org/W4389529169","doi":"https://doi.org/10.1109/icecs58634.2023.10382949"},"language":"en","primary_location":{"id":"doi:10.1109/icecs58634.2023.10382949","is_oa":false,"landing_page_url":"http://dx.doi.org/10.1109/icecs58634.2023.10382949","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2023 30th IEEE International Conference on Electronics, Circuits and Systems (ICECS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"https://hal.science/hal-04331999","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5092835379","display_name":"Diana Kalel","orcid":null},"institutions":[{"id":"https://openalex.org/I4210104693","display_name":"STMicroelectronics (France)","ror":"https://ror.org/01c74sd89","country_code":"FR","type":"company","lineage":["https://openalex.org/I131827901","https://openalex.org/I4210104693"]},{"id":"https://openalex.org/I899635006","display_name":"Universit\u00e9 Grenoble Alpes","ror":"https://ror.org/02rx3b187","country_code":"FR","type":"education","lineage":["https://openalex.org/I899635006"]},{"id":"https://openalex.org/I1294671590","display_name":"Centre National de la Recherche Scientifique","ror":"https://ror.org/02feahw73","country_code":"FR","type":"funder","lineage":["https://openalex.org/I1294671590"]},{"id":"https://openalex.org/I106785703","display_name":"Institut polytechnique de Grenoble","ror":"https://ror.org/05sbt2524","country_code":"FR","type":"education","lineage":["https://openalex.org/I106785703","https://openalex.org/I899635006"]}],"countries":["FR"],"is_corresponding":true,"raw_author_name":"Diana Kalel","raw_affiliation_strings":["STMicroelectronics, 12 Rue Jules Horowitz,Grenoble,France,38019","Univ. Grenoble Alpes, CNRS, Grenoble INP, TIMA, Institute of Engineering Univ. Grenoble Alpes, Grenoble, France"],"affiliations":[{"raw_affiliation_string":"STMicroelectronics, 12 Rue Jules Horowitz,Grenoble,France,38019","institution_ids":["https://openalex.org/I4210104693"]},{"raw_affiliation_string":"Univ. Grenoble Alpes, CNRS, Grenoble INP, TIMA, Institute of Engineering Univ. Grenoble Alpes, Grenoble, France","institution_ids":["https://openalex.org/I106785703","https://openalex.org/I899635006","https://openalex.org/I1294671590"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5069426138","display_name":"Jean-Christophe Brignone","orcid":null},"institutions":[{"id":"https://openalex.org/I4210104693","display_name":"STMicroelectronics (France)","ror":"https://ror.org/01c74sd89","country_code":"FR","type":"company","lineage":["https://openalex.org/I131827901","https://openalex.org/I4210104693"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Jean-Christophe Brignone","raw_affiliation_strings":["STMicroelectronics, 12 Rue Jules Horowitz,Grenoble,France,38019"],"affiliations":[{"raw_affiliation_string":"STMicroelectronics, 12 Rue Jules Horowitz,Grenoble,France,38019","institution_ids":["https://openalex.org/I4210104693"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5038428972","display_name":"Laurent Fesquet","orcid":"https://orcid.org/0000-0002-6045-8510"},"institutions":[{"id":"https://openalex.org/I106785703","display_name":"Institut polytechnique de Grenoble","ror":"https://ror.org/05sbt2524","country_code":"FR","type":"education","lineage":["https://openalex.org/I106785703","https://openalex.org/I899635006"]},{"id":"https://openalex.org/I899635006","display_name":"Universit\u00e9 Grenoble Alpes","ror":"https://ror.org/02rx3b187","country_code":"FR","type":"education","lineage":["https://openalex.org/I899635006"]},{"id":"https://openalex.org/I1294671590","display_name":"Centre National de la Recherche Scientifique","ror":"https://ror.org/02feahw73","country_code":"FR","type":"funder","lineage":["https://openalex.org/I1294671590"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Laurent Fesquet","raw_affiliation_strings":["Univ. Grenoble Alpes, CNRS, Grenoble INP, TIMA, Institute of Engineering Univ. Grenoble Alpes,Grenoble,France,38000"],"affiliations":[{"raw_affiliation_string":"Univ. Grenoble Alpes, CNRS, Grenoble INP, TIMA, Institute of Engineering Univ. Grenoble Alpes,Grenoble,France,38000","institution_ids":["https://openalex.org/I1294671590","https://openalex.org/I899635006","https://openalex.org/I106785703"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5067330751","display_name":"Katell Morin-Allory","orcid":null},"institutions":[{"id":"https://openalex.org/I1294671590","display_name":"Centre National de la Recherche Scientifique","ror":"https://ror.org/02feahw73","country_code":"FR","type":"funder","lineage":["https://openalex.org/I1294671590"]},{"id":"https://openalex.org/I106785703","display_name":"Institut polytechnique de Grenoble","ror":"https://ror.org/05sbt2524","country_code":"FR","type":"education","lineage":["https://openalex.org/I106785703","https://openalex.org/I899635006"]},{"id":"https://openalex.org/I899635006","display_name":"Universit\u00e9 Grenoble Alpes","ror":"https://ror.org/02rx3b187","country_code":"FR","type":"education","lineage":["https://openalex.org/I899635006"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Katell Morin-Allory","raw_affiliation_strings":["Univ. Grenoble Alpes, CNRS, Grenoble INP, TIMA, Institute of Engineering Univ. Grenoble Alpes,Grenoble,France,38000"],"affiliations":[{"raw_affiliation_string":"Univ. Grenoble Alpes, CNRS, Grenoble INP, TIMA, Institute of Engineering Univ. Grenoble Alpes,Grenoble,France,38000","institution_ids":["https://openalex.org/I1294671590","https://openalex.org/I899635006","https://openalex.org/I106785703"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5092835379"],"corresponding_institution_ids":["https://openalex.org/I106785703","https://openalex.org/I1294671590","https://openalex.org/I4210104693","https://openalex.org/I899635006"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.15351516,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9976999759674072,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9976999759674072,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9965999722480774,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9918000102043152,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/asynchronous-communication","display_name":"Asynchronous communication","score":0.8416532278060913},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8225485682487488},{"id":"https://openalex.org/keywords/synchronization","display_name":"Synchronization (alternating current)","score":0.741227388381958},{"id":"https://openalex.org/keywords/clock-skew","display_name":"Clock skew","score":0.717836856842041},{"id":"https://openalex.org/keywords/clock-synchronization","display_name":"Clock synchronization","score":0.6592466235160828},{"id":"https://openalex.org/keywords/clock-domain-crossing","display_name":"Clock domain crossing","score":0.6508201360702515},{"id":"https://openalex.org/keywords/skew","display_name":"Skew","score":0.6307435631752014},{"id":"https://openalex.org/keywords/asynchronous-system","display_name":"Asynchronous system","score":0.5946450233459473},{"id":"https://openalex.org/keywords/reset","display_name":"Reset (finance)","score":0.560523271560669},{"id":"https://openalex.org/keywords/domain","display_name":"Domain (mathematical analysis)","score":0.5542925596237183},{"id":"https://openalex.org/keywords/clock-drift","display_name":"Clock drift","score":0.5194680094718933},{"id":"https://openalex.org/keywords/static-timing-analysis","display_name":"Static timing analysis","score":0.44278568029403687},{"id":"https://openalex.org/keywords/stability","display_name":"Stability (learning theory)","score":0.42280715703964233},{"id":"https://openalex.org/keywords/digital-clock-manager","display_name":"Digital clock manager","score":0.42150625586509705},{"id":"https://openalex.org/keywords/synchronizer","display_name":"Synchronizer","score":0.420881986618042},{"id":"https://openalex.org/keywords/real-time-computing","display_name":"Real-time computing","score":0.41518664360046387},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3309810161590576},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.31880900263786316},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.26685309410095215},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.19502663612365723},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.10460755228996277},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.10365438461303711}],"concepts":[{"id":"https://openalex.org/C151319957","wikidata":"https://www.wikidata.org/wiki/Q752739","display_name":"Asynchronous communication","level":2,"score":0.8416532278060913},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8225485682487488},{"id":"https://openalex.org/C2778562939","wikidata":"https://www.wikidata.org/wiki/Q1298791","display_name":"Synchronization (alternating current)","level":3,"score":0.741227388381958},{"id":"https://openalex.org/C60501442","wikidata":"https://www.wikidata.org/wiki/Q4382014","display_name":"Clock skew","level":4,"score":0.717836856842041},{"id":"https://openalex.org/C129891060","wikidata":"https://www.wikidata.org/wiki/Q1513059","display_name":"Clock synchronization","level":4,"score":0.6592466235160828},{"id":"https://openalex.org/C127204226","wikidata":"https://www.wikidata.org/wiki/Q5134799","display_name":"Clock domain crossing","level":5,"score":0.6508201360702515},{"id":"https://openalex.org/C43711488","wikidata":"https://www.wikidata.org/wiki/Q7534783","display_name":"Skew","level":2,"score":0.6307435631752014},{"id":"https://openalex.org/C7923308","wikidata":"https://www.wikidata.org/wiki/Q4812211","display_name":"Asynchronous system","level":5,"score":0.5946450233459473},{"id":"https://openalex.org/C2779795794","wikidata":"https://www.wikidata.org/wiki/Q7315343","display_name":"Reset (finance)","level":2,"score":0.560523271560669},{"id":"https://openalex.org/C36503486","wikidata":"https://www.wikidata.org/wiki/Q11235244","display_name":"Domain (mathematical analysis)","level":2,"score":0.5542925596237183},{"id":"https://openalex.org/C155837451","wikidata":"https://www.wikidata.org/wiki/Q1069144","display_name":"Clock drift","level":5,"score":0.5194680094718933},{"id":"https://openalex.org/C93682380","wikidata":"https://www.wikidata.org/wiki/Q2025226","display_name":"Static timing analysis","level":2,"score":0.44278568029403687},{"id":"https://openalex.org/C112972136","wikidata":"https://www.wikidata.org/wiki/Q7595718","display_name":"Stability (learning theory)","level":2,"score":0.42280715703964233},{"id":"https://openalex.org/C113074038","wikidata":"https://www.wikidata.org/wiki/Q5276052","display_name":"Digital clock manager","level":5,"score":0.42150625586509705},{"id":"https://openalex.org/C66727535","wikidata":"https://www.wikidata.org/wiki/Q7662199","display_name":"Synchronizer","level":2,"score":0.420881986618042},{"id":"https://openalex.org/C79403827","wikidata":"https://www.wikidata.org/wiki/Q3988","display_name":"Real-time computing","level":1,"score":0.41518664360046387},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3309810161590576},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.31880900263786316},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.26685309410095215},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.19502663612365723},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.10460755228996277},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.10365438461303711},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C106159729","wikidata":"https://www.wikidata.org/wiki/Q2294553","display_name":"Financial economics","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0},{"id":"https://openalex.org/C119857082","wikidata":"https://www.wikidata.org/wiki/Q2539","display_name":"Machine learning","level":1,"score":0.0},{"id":"https://openalex.org/C127162648","wikidata":"https://www.wikidata.org/wiki/Q16858953","display_name":"Channel (broadcasting)","level":2,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/icecs58634.2023.10382949","is_oa":false,"landing_page_url":"http://dx.doi.org/10.1109/icecs58634.2023.10382949","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2023 30th IEEE International Conference on Electronics, Circuits and Systems (ICECS)","raw_type":"proceedings-article"},{"id":"pmh:oai:HAL:hal-04331999v1","is_oa":true,"landing_page_url":"https://hal.science/hal-04331999","pdf_url":null,"source":{"id":"https://openalex.org/S4406922461","display_name":"SPIRE - Sciences Po Institutional REpository","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by-nc","license_id":"https://openalex.org/licenses/cc-by-nc","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"IEEELink","raw_type":"Conference papers"}],"best_oa_location":{"id":"pmh:oai:HAL:hal-04331999v1","is_oa":true,"landing_page_url":"https://hal.science/hal-04331999","pdf_url":null,"source":{"id":"https://openalex.org/S4406922461","display_name":"SPIRE - Sciences Po Institutional REpository","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by-nc","license_id":"https://openalex.org/licenses/cc-by-nc","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"IEEELink","raw_type":"Conference papers"},"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":5,"referenced_works":["https://openalex.org/W2166550812","https://openalex.org/W3143326883","https://openalex.org/W4236620879","https://openalex.org/W6606565722","https://openalex.org/W6669868957"],"related_works":["https://openalex.org/W1842357617","https://openalex.org/W1497331638","https://openalex.org/W2292909929","https://openalex.org/W853533475","https://openalex.org/W2117541676","https://openalex.org/W2056489071","https://openalex.org/W60672686","https://openalex.org/W2787237207","https://openalex.org/W1966845705","https://openalex.org/W2477469844"],"abstract_inverted_index":{"Industrial":[0],"circuits":[1],"are":[2,37,59,84],"increasing":[3],"in":[4,41],"size":[5],"and":[6,23,54,80],"complexity":[7],"every":[8],"day,":[9],"making":[10],"it":[11],"very":[12],"difficult":[13],"to":[14,51,71,93,109,130],"propagate":[15],"one":[16],"low-skew":[17],"clock.":[18],"To":[19],"overcome":[20],"this":[21],"problem,":[22],"achieve":[24],"a":[25,118],"certain":[26],"level":[27],"of":[28,62,65,113],"power":[29,55],"optimization,":[30],"Globally":[31],"Asynchronous":[32],"Locally":[33],"Synchronous":[34],"(GALS)":[35],"systems":[36],"widely":[38],"used.":[39],"However,":[40],"these":[42],"asynchronous":[43],"multi-clock":[44],"systems,":[45],"some":[46,90],"other":[47],"problems":[48],"arise":[49],"due":[50],"clock,":[52],"reset,":[53],"domain":[56],"crossing;":[57],"they":[58,83],"the":[60,74,94,102],"subject":[61],"different":[63],"types":[64,112],"exhaustive":[66],"verification.":[67],"The":[68],"goal":[69],"is":[70,128],"detect":[72,110,132],"all":[73,111,133],"Clock":[75],"Domain":[76],"Crossing":[77],"(CDC)":[78],"signals":[79],"ensure":[81],"that":[82,121],"properly":[85],"synchronized.":[86],"We":[87,116],"have":[88],"noticed":[89],"limitations":[91],"related":[92],"CDC":[95],"data":[96],"paths":[97],"detection":[98],"at":[99],"RT-level":[100],"by":[101],"industrial":[103],"static":[104],"verification":[105],"tools.":[106],"They":[107],"fail":[108],"synchronization":[114,135],"protocols.":[115],"propose":[117],"new":[119],"approach":[120],"does":[122],"not":[123],"depend":[124],"on":[125],"them.":[126],"It":[127],"able":[129],"correctly":[131],"control":[134],"signals.":[136]},"counts_by_year":[],"updated_date":"2026-04-04T16:13:02.066488","created_date":"2025-10-10T00:00:00"}
