{"id":"https://openalex.org/W4390693351","doi":"https://doi.org/10.1109/icecs58634.2023.10382815","title":"A New Source-Coupled Logic Technique: ALSCL","display_name":"A New Source-Coupled Logic Technique: ALSCL","publication_year":2023,"publication_date":"2023-12-04","ids":{"openalex":"https://openalex.org/W4390693351","doi":"https://doi.org/10.1109/icecs58634.2023.10382815"},"language":"en","primary_location":{"id":"doi:10.1109/icecs58634.2023.10382815","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecs58634.2023.10382815","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2023 30th IEEE International Conference on Electronics, Circuits and Systems (ICECS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5038302966","display_name":"U\u011fur \u00c7ini","orcid":"https://orcid.org/0000-0002-9827-7993"},"institutions":[{"id":"https://openalex.org/I1281256770","display_name":"\u00dcsk\u00fcdar University","ror":"https://ror.org/02dzjmc73","country_code":"TR","type":"education","lineage":["https://openalex.org/I1281256770"]}],"countries":["TR"],"is_corresponding":true,"raw_author_name":"Ugur Cini","raw_affiliation_strings":["Uskudar University,Dept. of Electrical &#x0026; Electronics Engineering,Istanbul,Turkey"],"affiliations":[{"raw_affiliation_string":"Uskudar University,Dept. of Electrical &#x0026; Electronics Engineering,Istanbul,Turkey","institution_ids":["https://openalex.org/I1281256770"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5100328347","display_name":"Shuai Wang","orcid":"https://orcid.org/0000-0003-2997-1030"},"institutions":[{"id":"https://openalex.org/I4210119559","display_name":"Taiwan Semiconductor Manufacturing Company (China)","ror":"https://ror.org/02s0wcj29","country_code":"CN","type":"company","lineage":["https://openalex.org/I4210119559","https://openalex.org/I4210120917"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Shuai Wang","raw_affiliation_strings":["MICROTERA (Guangzhou) Semiconductor Co., Ltd Unit1101/F11 Build. A, No18 Science Boulevard,Guangzhou Science Park,China","MICROTERA (Guangzhou) Semiconductor Co., Ltd Unit1101/F11 Build. A, No18 Science Boulevard, Guangzhou Science Park, China"],"affiliations":[{"raw_affiliation_string":"MICROTERA (Guangzhou) Semiconductor Co., Ltd Unit1101/F11 Build. A, No18 Science Boulevard,Guangzhou Science Park,China","institution_ids":["https://openalex.org/I4210119559"]},{"raw_affiliation_string":"MICROTERA (Guangzhou) Semiconductor Co., Ltd Unit1101/F11 Build. A, No18 Science Boulevard, Guangzhou Science Park, China","institution_ids":["https://openalex.org/I4210119559"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5038302966"],"corresponding_institution_ids":["https://openalex.org/I1281256770"],"apc_list":null,"apc_paid":null,"fwci":0.1339,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.4805749,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":91,"max":95},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6496222615242004},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.5867164134979248},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5821718573570251},{"id":"https://openalex.org/keywords/spice","display_name":"Spice","score":0.5679953694343567},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.522655725479126},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.5166873931884766},{"id":"https://openalex.org/keywords/logic-optimization","display_name":"Logic optimization","score":0.5046628713607788},{"id":"https://openalex.org/keywords/pass-transistor-logic","display_name":"Pass transistor logic","score":0.47713398933410645},{"id":"https://openalex.org/keywords/sequential-logic","display_name":"Sequential logic","score":0.44964277744293213},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.4426233172416687},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.3355286121368408},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.24713703989982605},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.22426342964172363},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.20698562264442444},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.1748799979686737}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6496222615242004},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.5867164134979248},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5821718573570251},{"id":"https://openalex.org/C2780077345","wikidata":"https://www.wikidata.org/wiki/Q16891888","display_name":"Spice","level":2,"score":0.5679953694343567},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.522655725479126},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.5166873931884766},{"id":"https://openalex.org/C28449271","wikidata":"https://www.wikidata.org/wiki/Q6667469","display_name":"Logic optimization","level":4,"score":0.5046628713607788},{"id":"https://openalex.org/C198521697","wikidata":"https://www.wikidata.org/wiki/Q7142438","display_name":"Pass transistor logic","level":4,"score":0.47713398933410645},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.44964277744293213},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.4426233172416687},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3355286121368408},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.24713703989982605},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.22426342964172363},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.20698562264442444},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.1748799979686737}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/icecs58634.2023.10382815","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecs58634.2023.10382815","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2023 30th IEEE International Conference on Electronics, Circuits and Systems (ICECS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":9,"referenced_works":["https://openalex.org/W1566744640","https://openalex.org/W2030822983","https://openalex.org/W2039325969","https://openalex.org/W2097154741","https://openalex.org/W2118575401","https://openalex.org/W2135286216","https://openalex.org/W3134041270","https://openalex.org/W3163176851","https://openalex.org/W4378639301"],"related_works":["https://openalex.org/W3129977055","https://openalex.org/W1966764473","https://openalex.org/W1553855433","https://openalex.org/W1488117239","https://openalex.org/W2386022279","https://openalex.org/W2098419840","https://openalex.org/W2152533674","https://openalex.org/W2991771859","https://openalex.org/W2006855068","https://openalex.org/W2356714888"],"abstract_inverted_index":{"In":[0,51],"this":[1],"work,":[2],"we":[3],"analyzed":[4],"some":[5],"of":[6,10,59,87],"the":[7,11,48,52,77,88,110],"design":[8,40,45,70,90],"aspects":[9],"newly":[12],"introduced":[13],"source-coupled":[14,31],"logic":[15,25,112],"family":[16],"as:":[17],"Active":[18],"Loaded":[19],"Source-Coupled":[20],"Logic":[21],"(ALSCL).":[22],"The":[23,73,92],"proposed":[24,78,111],"requires":[26],"single-ended":[27],"routing":[28],"whereas":[29],"classical":[30],"circuits":[32,93],"are":[33,94],"differential":[34],"in":[35],"nature.":[36],"It":[37],"has":[38,43],"straightforward":[39],"methodology":[41],"and":[42,56,66,101,105],"analog-friendly":[44,89],"advantages":[46],"at":[47],"same":[49],"time.":[50],"paper,":[53],"working":[54],"principles":[55],"delay":[57],"modeling":[58],"ALSCL":[60,79],"is":[61,71],"elaborated,":[62],"also":[63],"a":[64,82],"D-Latch":[65],"D-type":[67],"master-slave":[68],"flip-flop":[69],"provided.":[72],"results":[74,108],"show":[75],"that":[76],"can":[80],"be":[81],"direct":[83],"replacement":[84],"for":[85,98,109],"many":[86],"blocks.":[91],"simulated":[95],"using":[96],"SPICE":[97],"0.35":[99],"$\\mu$m":[100,103],"0.18":[102],"technologies":[104],"provide":[106],"promising":[107],"family.":[113]},"counts_by_year":[{"year":2025,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
