{"id":"https://openalex.org/W4390693267","doi":"https://doi.org/10.1109/icecs58634.2023.10382774","title":"Design and Implementation of a RISC-V core with a Flexible Pipeline for Design Space Exploration","display_name":"Design and Implementation of a RISC-V core with a Flexible Pipeline for Design Space Exploration","publication_year":2023,"publication_date":"2023-12-04","ids":{"openalex":"https://openalex.org/W4390693267","doi":"https://doi.org/10.1109/icecs58634.2023.10382774"},"language":"en","primary_location":{"id":"doi:10.1109/icecs58634.2023.10382774","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecs58634.2023.10382774","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2023 30th IEEE International Conference on Electronics, Circuits and Systems (ICECS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5092519490","display_name":"Jonathan Saussereau","orcid":null},"institutions":[{"id":"https://openalex.org/I1294671590","display_name":"Centre National de la Recherche Scientifique","ror":"https://ror.org/02feahw73","country_code":"FR","type":"government","lineage":["https://openalex.org/I1294671590"]},{"id":"https://openalex.org/I4210157089","display_name":"Laboratoire de l'Int\u00e9gration du Mat\u00e9riau au Syst\u00e8me","ror":"https://ror.org/04nabhy78","country_code":"FR","type":"facility","lineage":["https://openalex.org/I1294671590","https://openalex.org/I1294671590","https://openalex.org/I15057530","https://openalex.org/I4210091158","https://openalex.org/I4210095849","https://openalex.org/I4210157089","https://openalex.org/I4210160189"]},{"id":"https://openalex.org/I4210160189","display_name":"Institut Polytechnique de Bordeaux","ror":"https://ror.org/054qv7y42","country_code":"FR","type":"education","lineage":["https://openalex.org/I4210160189"]}],"countries":["FR"],"is_corresponding":true,"raw_author_name":"Jonathan Saussereau","raw_affiliation_strings":["Université de Bordeaux, Bordeaux INP, Laboratoire IMS, UMR CNRS 5218,France"],"affiliations":[{"raw_affiliation_string":"Université de Bordeaux, Bordeaux INP, Laboratoire IMS, UMR CNRS 5218,France","institution_ids":["https://openalex.org/I4210157089","https://openalex.org/I4210160189","https://openalex.org/I1294671590"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5031142198","display_name":"Christophe J\u00e9go","orcid":"https://orcid.org/0000-0001-5964-6277"},"institutions":[{"id":"https://openalex.org/I1294671590","display_name":"Centre National de la Recherche Scientifique","ror":"https://ror.org/02feahw73","country_code":"FR","type":"government","lineage":["https://openalex.org/I1294671590"]},{"id":"https://openalex.org/I4210157089","display_name":"Laboratoire de l'Int\u00e9gration du Mat\u00e9riau au Syst\u00e8me","ror":"https://ror.org/04nabhy78","country_code":"FR","type":"facility","lineage":["https://openalex.org/I1294671590","https://openalex.org/I1294671590","https://openalex.org/I15057530","https://openalex.org/I4210091158","https://openalex.org/I4210095849","https://openalex.org/I4210157089","https://openalex.org/I4210160189"]},{"id":"https://openalex.org/I4210160189","display_name":"Institut Polytechnique de Bordeaux","ror":"https://ror.org/054qv7y42","country_code":"FR","type":"education","lineage":["https://openalex.org/I4210160189"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Christophe Jego","raw_affiliation_strings":["Université de Bordeaux, Bordeaux INP, Laboratoire IMS, UMR CNRS 5218,France"],"affiliations":[{"raw_affiliation_string":"Université de Bordeaux, Bordeaux INP, Laboratoire IMS, UMR CNRS 5218,France","institution_ids":["https://openalex.org/I4210157089","https://openalex.org/I4210160189","https://openalex.org/I1294671590"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5000320277","display_name":"Camille Leroux","orcid":"https://orcid.org/0000-0002-4984-3485"},"institutions":[{"id":"https://openalex.org/I1294671590","display_name":"Centre National de la Recherche Scientifique","ror":"https://ror.org/02feahw73","country_code":"FR","type":"government","lineage":["https://openalex.org/I1294671590"]},{"id":"https://openalex.org/I4210157089","display_name":"Laboratoire de l'Int\u00e9gration du Mat\u00e9riau au Syst\u00e8me","ror":"https://ror.org/04nabhy78","country_code":"FR","type":"facility","lineage":["https://openalex.org/I1294671590","https://openalex.org/I1294671590","https://openalex.org/I15057530","https://openalex.org/I4210091158","https://openalex.org/I4210095849","https://openalex.org/I4210157089","https://openalex.org/I4210160189"]},{"id":"https://openalex.org/I4210160189","display_name":"Institut Polytechnique de Bordeaux","ror":"https://ror.org/054qv7y42","country_code":"FR","type":"education","lineage":["https://openalex.org/I4210160189"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Camille Leroux","raw_affiliation_strings":["Université de Bordeaux, Bordeaux INP, Laboratoire IMS, UMR CNRS 5218,France"],"affiliations":[{"raw_affiliation_string":"Université de Bordeaux, Bordeaux INP, Laboratoire IMS, UMR CNRS 5218,France","institution_ids":["https://openalex.org/I4210157089","https://openalex.org/I4210160189","https://openalex.org/I1294671590"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5109586805","display_name":"Jean-Baptiste B\u00e9gueret","orcid":null},"institutions":[{"id":"https://openalex.org/I1294671590","display_name":"Centre National de la Recherche Scientifique","ror":"https://ror.org/02feahw73","country_code":"FR","type":"government","lineage":["https://openalex.org/I1294671590"]},{"id":"https://openalex.org/I4210157089","display_name":"Laboratoire de l'Int\u00e9gration du Mat\u00e9riau au Syst\u00e8me","ror":"https://ror.org/04nabhy78","country_code":"FR","type":"facility","lineage":["https://openalex.org/I1294671590","https://openalex.org/I1294671590","https://openalex.org/I15057530","https://openalex.org/I4210091158","https://openalex.org/I4210095849","https://openalex.org/I4210157089","https://openalex.org/I4210160189"]},{"id":"https://openalex.org/I4210160189","display_name":"Institut Polytechnique de Bordeaux","ror":"https://ror.org/054qv7y42","country_code":"FR","type":"education","lineage":["https://openalex.org/I4210160189"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Jean-Baptiste Begueret","raw_affiliation_strings":["Université de Bordeaux, Bordeaux INP, Laboratoire IMS, UMR CNRS 5218,France"],"affiliations":[{"raw_affiliation_string":"Université de Bordeaux, Bordeaux INP, Laboratoire IMS, UMR CNRS 5218,France","institution_ids":["https://openalex.org/I4210157089","https://openalex.org/I4210160189","https://openalex.org/I1294671590"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5092519490"],"corresponding_institution_ids":["https://openalex.org/I1294671590","https://openalex.org/I4210157089","https://openalex.org/I4210160189"],"apc_list":null,"apc_paid":null,"fwci":0.4016,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.62135651,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"5"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/pipeline","display_name":"Pipeline (software)","score":0.8684487342834473},{"id":"https://openalex.org/keywords/design-space-exploration","display_name":"Design space exploration","score":0.725507915019989},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6882216930389404},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.6661736369132996},{"id":"https://openalex.org/keywords/application-specific-integrated-circuit","display_name":"Application-specific integrated circuit","score":0.6655128598213196},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6344490647315979},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5876262784004211},{"id":"https://openalex.org/keywords/reduced-instruction-set-computing","display_name":"Reduced instruction set computing","score":0.5668963193893433},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.5630084276199341},{"id":"https://openalex.org/keywords/microarchitecture","display_name":"Microarchitecture","score":0.5373706817626953},{"id":"https://openalex.org/keywords/domain","display_name":"Domain (mathematical analysis)","score":0.42922842502593994},{"id":"https://openalex.org/keywords/instruction-set","display_name":"Instruction set","score":0.38234323263168335},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.22651800513267517},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.13714522123336792}],"concepts":[{"id":"https://openalex.org/C43521106","wikidata":"https://www.wikidata.org/wiki/Q2165493","display_name":"Pipeline (software)","level":2,"score":0.8684487342834473},{"id":"https://openalex.org/C2776221188","wikidata":"https://www.wikidata.org/wiki/Q21072556","display_name":"Design space exploration","level":2,"score":0.725507915019989},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6882216930389404},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.6661736369132996},{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.6655128598213196},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6344490647315979},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5876262784004211},{"id":"https://openalex.org/C126298526","wikidata":"https://www.wikidata.org/wiki/Q189376","display_name":"Reduced instruction set computing","level":3,"score":0.5668963193893433},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.5630084276199341},{"id":"https://openalex.org/C107598950","wikidata":"https://www.wikidata.org/wiki/Q259864","display_name":"Microarchitecture","level":2,"score":0.5373706817626953},{"id":"https://openalex.org/C36503486","wikidata":"https://www.wikidata.org/wiki/Q11235244","display_name":"Domain (mathematical analysis)","level":2,"score":0.42922842502593994},{"id":"https://openalex.org/C202491316","wikidata":"https://www.wikidata.org/wiki/Q272683","display_name":"Instruction set","level":2,"score":0.38234323263168335},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.22651800513267517},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.13714522123336792},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/icecs58634.2023.10382774","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecs58634.2023.10382774","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2023 30th IEEE International Conference on Electronics, Circuits and Systems (ICECS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":8,"referenced_works":["https://openalex.org/W220440441","https://openalex.org/W1983394510","https://openalex.org/W2004340162","https://openalex.org/W2155097923","https://openalex.org/W2769218998","https://openalex.org/W2916672784","https://openalex.org/W4244264053","https://openalex.org/W4385080211"],"related_works":["https://openalex.org/W4386869637","https://openalex.org/W2538644970","https://openalex.org/W4376881175","https://openalex.org/W4200599950","https://openalex.org/W4310584696","https://openalex.org/W4385730960","https://openalex.org/W2169880332","https://openalex.org/W4237840813","https://openalex.org/W4364295250","https://openalex.org/W2114044010"],"abstract_inverted_index":{"This":[0],"paper":[1],"addresses":[2],"the":[3,11,31,44,50,75,85,97,101,104,114],"need":[4],"for":[5],"customizable":[6,39],"processor":[7],"architectures":[8,56],"by":[9,36,99],"presenting":[10],"design":[12,32],"and":[13,18,61,68,110,118],"implementation,":[14],"on":[15,80],"both":[16],"FPGA":[17],"ASIC":[19],"devices,":[20],"of":[21,41,54,77,87,103,116],"a":[22,38,62],"flexible":[23],"RISC-V":[24],"in-order":[25],"pipeline":[26,45,78],"core.":[27],"The":[28,47,93],"study":[29,71],"expands":[30],"space":[33],"exploration":[34],"possibilities":[35],"introducing":[37],"number":[40],"stages":[42],"in":[43,90,113],"architecture.":[46],"methodology":[48],"leverages":[49],"fundamental":[51],"building":[52],"blocks":[53],"non-pipelined":[55],"while":[57,82],"incorporating":[58],"different":[59],"interconnections":[60],"specific":[63],"control":[64],"unit.":[65],"Through":[66],"evaluation":[67],"analysis,":[69],"this":[70],"provides":[72],"insights":[73],"into":[74],"impact":[76],"architecture":[79,91],"performance,":[81],"also":[83],"highlighting":[84],"advantages":[86],"non-pipeline":[88],"processors":[89],"design.":[92],"findings":[94],"contribute":[95],"to":[96],"field":[98],"enabling":[100],"identification":[102],"optimal":[105],"architecture,":[106],"considering":[107],"application":[108],"constraints":[109],"target":[111],"technology,":[112],"domain":[115],"size-optimized":[117],"low-power":[119],"CPUs.":[120]},"counts_by_year":[{"year":2025,"cited_by_count":2},{"year":2024,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}