{"id":"https://openalex.org/W3117240492","doi":"https://doi.org/10.1109/icecs49266.2020.9294942","title":"A Fast and Accurate True Event-driven Phase Locked Loop Model","display_name":"A Fast and Accurate True Event-driven Phase Locked Loop Model","publication_year":2020,"publication_date":"2020-11-23","ids":{"openalex":"https://openalex.org/W3117240492","doi":"https://doi.org/10.1109/icecs49266.2020.9294942","mag":"3117240492"},"language":"en","primary_location":{"id":"doi:10.1109/icecs49266.2020.9294942","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecs49266.2020.9294942","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5021743529","display_name":"Christoph Beyerstedt","orcid":null},"institutions":[{"id":"https://openalex.org/I887968799","display_name":"RWTH Aachen University","ror":"https://ror.org/04xfq0f34","country_code":"DE","type":"education","lineage":["https://openalex.org/I887968799"]}],"countries":["DE"],"is_corresponding":true,"raw_author_name":"Christoph Beyerstedt","raw_affiliation_strings":["Chair of Integrated Analog Circuits and RF Systems, RWTH Aachen University, Aachen, Germany"],"affiliations":[{"raw_affiliation_string":"Chair of Integrated Analog Circuits and RF Systems, RWTH Aachen University, Aachen, Germany","institution_ids":["https://openalex.org/I887968799"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5066227386","display_name":"Jonas Meier","orcid":null},"institutions":[{"id":"https://openalex.org/I887968799","display_name":"RWTH Aachen University","ror":"https://ror.org/04xfq0f34","country_code":"DE","type":"education","lineage":["https://openalex.org/I887968799"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Jonas Meier","raw_affiliation_strings":["Chair of Integrated Analog Circuits and RF Systems, RWTH Aachen University, Aachen, Germany"],"affiliations":[{"raw_affiliation_string":"Chair of Integrated Analog Circuits and RF Systems, RWTH Aachen University, Aachen, Germany","institution_ids":["https://openalex.org/I887968799"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5003604689","display_name":"Fabian Speicher","orcid":null},"institutions":[{"id":"https://openalex.org/I887968799","display_name":"RWTH Aachen University","ror":"https://ror.org/04xfq0f34","country_code":"DE","type":"education","lineage":["https://openalex.org/I887968799"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Fabian Speicher","raw_affiliation_strings":["Chair of Integrated Analog Circuits and RF Systems, RWTH Aachen University, Aachen, Germany"],"affiliations":[{"raw_affiliation_string":"Chair of Integrated Analog Circuits and RF Systems, RWTH Aachen University, Aachen, Germany","institution_ids":["https://openalex.org/I887968799"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5047212288","display_name":"Markus Scholl","orcid":null},"institutions":[{"id":"https://openalex.org/I887968799","display_name":"RWTH Aachen University","ror":"https://ror.org/04xfq0f34","country_code":"DE","type":"education","lineage":["https://openalex.org/I887968799"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Markus Scholl","raw_affiliation_strings":["Chair of Integrated Analog Circuits and RF Systems, RWTH Aachen University, Aachen, Germany"],"affiliations":[{"raw_affiliation_string":"Chair of Integrated Analog Circuits and RF Systems, RWTH Aachen University, Aachen, Germany","institution_ids":["https://openalex.org/I887968799"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5056126865","display_name":"Daniel Blase","orcid":null},"institutions":[{"id":"https://openalex.org/I887968799","display_name":"RWTH Aachen University","ror":"https://ror.org/04xfq0f34","country_code":"DE","type":"education","lineage":["https://openalex.org/I887968799"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Daniel Blase","raw_affiliation_strings":["Chair of Integrated Analog Circuits and RF Systems, RWTH Aachen University, Aachen, Germany"],"affiliations":[{"raw_affiliation_string":"Chair of Integrated Analog Circuits and RF Systems, RWTH Aachen University, Aachen, Germany","institution_ids":["https://openalex.org/I887968799"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5033528054","display_name":"Ralf Wunderlich","orcid":"https://orcid.org/0000-0001-5841-6293"},"institutions":[{"id":"https://openalex.org/I887968799","display_name":"RWTH Aachen University","ror":"https://ror.org/04xfq0f34","country_code":"DE","type":"education","lineage":["https://openalex.org/I887968799"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Ralf Wunderlich","raw_affiliation_strings":["Chair of Integrated Analog Circuits and RF Systems, RWTH Aachen University, Aachen, Germany"],"affiliations":[{"raw_affiliation_string":"Chair of Integrated Analog Circuits and RF Systems, RWTH Aachen University, Aachen, Germany","institution_ids":["https://openalex.org/I887968799"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5039003474","display_name":"Stefan Heinen","orcid":"https://orcid.org/0009-0001-7568-8116"},"institutions":[{"id":"https://openalex.org/I887968799","display_name":"RWTH Aachen University","ror":"https://ror.org/04xfq0f34","country_code":"DE","type":"education","lineage":["https://openalex.org/I887968799"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Stefan Heinen","raw_affiliation_strings":["Chair of Integrated Analog Circuits and RF Systems, RWTH Aachen University, Aachen, Germany"],"affiliations":[{"raw_affiliation_string":"Chair of Integrated Analog Circuits and RF Systems, RWTH Aachen University, Aachen, Germany","institution_ids":["https://openalex.org/I887968799"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":7,"corresponding_author_ids":["https://openalex.org/A5021743529"],"corresponding_institution_ids":["https://openalex.org/I887968799"],"apc_list":null,"apc_paid":null,"fwci":0.5137,"has_fulltext":false,"cited_by_count":6,"citation_normalized_percentile":{"value":0.65924428,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":98},"biblio":{"volume":null,"issue":null,"first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"Phase-locked loop","score":0.8116294145584106},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7098369598388672},{"id":"https://openalex.org/keywords/correctness","display_name":"Correctness","score":0.6869605779647827},{"id":"https://openalex.org/keywords/waveform","display_name":"Waveform","score":0.6309716701507568},{"id":"https://openalex.org/keywords/signal","display_name":"SIGNAL (programming language)","score":0.5757904648780823},{"id":"https://openalex.org/keywords/discrete-event-simulation","display_name":"Discrete event simulation","score":0.5237538814544678},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.516312301158905},{"id":"https://openalex.org/keywords/mixed-signal-integrated-circuit","display_name":"Mixed-signal integrated circuit","score":0.44679170846939087},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.3861321210861206},{"id":"https://openalex.org/keywords/control-theory","display_name":"Control theory (sociology)","score":0.3257291316986084},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.24872875213623047},{"id":"https://openalex.org/keywords/simulation","display_name":"Simulation","score":0.18223628401756287},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.16387581825256348},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.14161229133605957}],"concepts":[{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.8116294145584106},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7098369598388672},{"id":"https://openalex.org/C55439883","wikidata":"https://www.wikidata.org/wiki/Q360812","display_name":"Correctness","level":2,"score":0.6869605779647827},{"id":"https://openalex.org/C197424946","wikidata":"https://www.wikidata.org/wiki/Q1165717","display_name":"Waveform","level":3,"score":0.6309716701507568},{"id":"https://openalex.org/C2779843651","wikidata":"https://www.wikidata.org/wiki/Q7390335","display_name":"SIGNAL (programming language)","level":2,"score":0.5757904648780823},{"id":"https://openalex.org/C147203929","wikidata":"https://www.wikidata.org/wiki/Q574814","display_name":"Discrete event simulation","level":2,"score":0.5237538814544678},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.516312301158905},{"id":"https://openalex.org/C62907940","wikidata":"https://www.wikidata.org/wiki/Q1541329","display_name":"Mixed-signal integrated circuit","level":3,"score":0.44679170846939087},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3861321210861206},{"id":"https://openalex.org/C47446073","wikidata":"https://www.wikidata.org/wiki/Q5165890","display_name":"Control theory (sociology)","level":3,"score":0.3257291316986084},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.24872875213623047},{"id":"https://openalex.org/C44154836","wikidata":"https://www.wikidata.org/wiki/Q45045","display_name":"Simulation","level":1,"score":0.18223628401756287},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.16387581825256348},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.14161229133605957},{"id":"https://openalex.org/C2775924081","wikidata":"https://www.wikidata.org/wiki/Q55608371","display_name":"Control (management)","level":2,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.0},{"id":"https://openalex.org/C554190296","wikidata":"https://www.wikidata.org/wiki/Q47528","display_name":"Radar","level":2,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/icecs49266.2020.9294942","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecs49266.2020.9294942","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":6,"referenced_works":["https://openalex.org/W2043696343","https://openalex.org/W2080279741","https://openalex.org/W2103089145","https://openalex.org/W2174676994","https://openalex.org/W2180303965","https://openalex.org/W2886246838"],"related_works":["https://openalex.org/W2359166095","https://openalex.org/W2334695394","https://openalex.org/W2390087637","https://openalex.org/W571305226","https://openalex.org/W2062418988","https://openalex.org/W2294477856","https://openalex.org/W2592492952","https://openalex.org/W2101750046","https://openalex.org/W2165051398","https://openalex.org/W568277441"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"a":[3,24,56,80,97],"fast":[4],"and":[5,85,104,108],"accurate":[6],"event-driven":[7],"modeling":[8],"approach":[9,76],"for":[10,88],"mixed-signal":[11],"phase":[12],"locked":[13],"loops":[14],"(PLLs).":[15],"To":[16],"generate":[17],"as":[18,22],"few":[19],"simulation":[20,72],"events":[21],"possible":[23],"signal":[25,57],"description":[26,84],"is":[27],"used,":[28],"which":[29],"utilizes":[30],"linear":[31],"combinations":[32],"of":[33,43],"analytical":[34],"basic":[35],"waveform":[36],"sequences":[37],"allowing":[38,63],"the":[39,44,60,66],"direct":[40],"algebraic":[41],"calculation":[42],"analog":[45],"circuit's":[46],"response":[47],"without":[48],"using":[49,79],"numeric":[50],"integration.":[51],"The":[52,74,91,102],"PLL":[53,67],"output":[54],"provides":[55],"described":[58],"in":[59],"spectral":[61],"domain":[62],"to":[64],"combine":[65],"model":[68,92],"with":[69],"advanced":[70],"RF":[71],"methods.":[73],"realized":[75],"was":[77,86,94,106],"implemented":[78],"mixed":[81],"System":[82],"Verilog/C++":[83],"used":[87],"verification":[89],"purpose.":[90],"correctness":[93],"verified":[95],"against":[96,110],"reference":[98],"transistor":[99],"level":[100],"simulation.":[101],"accuracy":[103],"speed-up":[105],"calculated":[107],"compared":[109],"other":[111],"approaches.":[112]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":5}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
