{"id":"https://openalex.org/W3117751879","doi":"https://doi.org/10.1109/icecs49266.2020.9294824","title":"A 10 Bit Phase-Interpolator-Based Digital-to-Phase Converter for Accurate Time Synchronization in Ethernet Applications","display_name":"A 10 Bit Phase-Interpolator-Based Digital-to-Phase Converter for Accurate Time Synchronization in Ethernet Applications","publication_year":2020,"publication_date":"2020-11-23","ids":{"openalex":"https://openalex.org/W3117751879","doi":"https://doi.org/10.1109/icecs49266.2020.9294824","mag":"3117751879"},"language":"en","primary_location":{"id":"doi:10.1109/icecs49266.2020.9294824","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecs49266.2020.9294824","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5064611852","display_name":"Simon Buhr","orcid":"https://orcid.org/0000-0002-6980-2648"},"institutions":[{"id":"https://openalex.org/I78650965","display_name":"Technische Universit\u00e4t Dresden","ror":"https://ror.org/042aqky30","country_code":"DE","type":"education","lineage":["https://openalex.org/I78650965"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Simon Buhr","raw_affiliation_strings":["Chair for Circuit Design and Network Theory, Technische Universit\u00e4t Dresden, Dresden, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Chair for Circuit Design and Network Theory, Technische Universit\u00e4t Dresden, Dresden, Germany","institution_ids":["https://openalex.org/I78650965"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5072097485","display_name":"Christian Hoyer","orcid":"https://orcid.org/0000-0003-2197-6080"},"institutions":[{"id":"https://openalex.org/I78650965","display_name":"Technische Universit\u00e4t Dresden","ror":"https://ror.org/042aqky30","country_code":"DE","type":"education","lineage":["https://openalex.org/I78650965"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Christian Hoyer","raw_affiliation_strings":["Chair for Circuit Design and Network Theory, Technische Universit\u00e4t Dresden, Dresden, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Chair for Circuit Design and Network Theory, Technische Universit\u00e4t Dresden, Dresden, Germany","institution_ids":["https://openalex.org/I78650965"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5026930933","display_name":"Martin Krei\u00dfig","orcid":"https://orcid.org/0000-0002-2773-9193"},"institutions":[{"id":"https://openalex.org/I78650965","display_name":"Technische Universit\u00e4t Dresden","ror":"https://ror.org/042aqky30","country_code":"DE","type":"education","lineage":["https://openalex.org/I78650965"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Martin Kreissig","raw_affiliation_strings":["Chair for Circuit Design and Network Theory, Technische Universit\u00e4t Dresden, Dresden, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Chair for Circuit Design and Network Theory, Technische Universit\u00e4t Dresden, Dresden, Germany","institution_ids":["https://openalex.org/I78650965"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5049816054","display_name":"Frank Ellinger","orcid":"https://orcid.org/0000-0001-6714-0479"},"institutions":[{"id":"https://openalex.org/I78650965","display_name":"Technische Universit\u00e4t Dresden","ror":"https://ror.org/042aqky30","country_code":"DE","type":"education","lineage":["https://openalex.org/I78650965"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Frank Ellinger","raw_affiliation_strings":["Chair for Circuit Design and Network Theory, Technische Universit\u00e4t Dresden, Dresden, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Chair for Circuit Design and Network Theory, Technische Universit\u00e4t Dresden, Dresden, Germany","institution_ids":["https://openalex.org/I78650965"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I78650965"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.23111744,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":95,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12216","display_name":"Network Time Synchronization Technologies","score":0.9904000163078308,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10299","display_name":"Photonic and Optical Devices","score":0.9869999885559082,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"Phase-locked loop","score":0.8361890316009521},{"id":"https://openalex.org/keywords/synchronization","display_name":"Synchronization (alternating current)","score":0.6158475875854492},{"id":"https://openalex.org/keywords/time-to-digital-converter","display_name":"Time-to-digital converter","score":0.5781328082084656},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5681135058403015},{"id":"https://openalex.org/keywords/transceiver","display_name":"Transceiver","score":0.5676531791687012},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5660337209701538},{"id":"https://openalex.org/keywords/ethernet","display_name":"Ethernet","score":0.5657931566238403},{"id":"https://openalex.org/keywords/clock-synchronization","display_name":"Clock synchronization","score":0.48427003622055054},{"id":"https://openalex.org/keywords/synchronous-ethernet","display_name":"Synchronous Ethernet","score":0.45046988129615784},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.30608105659484863},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.2677672207355499},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.2621521055698395},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.235006183385849},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.21652930974960327},{"id":"https://openalex.org/keywords/phase-noise","display_name":"Phase noise","score":0.21455731987953186},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.13896530866622925},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.09474477171897888}],"concepts":[{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.8361890316009521},{"id":"https://openalex.org/C2778562939","wikidata":"https://www.wikidata.org/wiki/Q1298791","display_name":"Synchronization (alternating current)","level":3,"score":0.6158475875854492},{"id":"https://openalex.org/C99594498","wikidata":"https://www.wikidata.org/wiki/Q2434524","display_name":"Time-to-digital converter","level":4,"score":0.5781328082084656},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5681135058403015},{"id":"https://openalex.org/C7720470","wikidata":"https://www.wikidata.org/wiki/Q954187","display_name":"Transceiver","level":3,"score":0.5676531791687012},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5660337209701538},{"id":"https://openalex.org/C172173386","wikidata":"https://www.wikidata.org/wiki/Q79984","display_name":"Ethernet","level":2,"score":0.5657931566238403},{"id":"https://openalex.org/C129891060","wikidata":"https://www.wikidata.org/wiki/Q1513059","display_name":"Clock synchronization","level":4,"score":0.48427003622055054},{"id":"https://openalex.org/C205215620","wikidata":"https://www.wikidata.org/wiki/Q7662206","display_name":"Synchronous Ethernet","level":3,"score":0.45046988129615784},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.30608105659484863},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.2677672207355499},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.2621521055698395},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.235006183385849},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.21652930974960327},{"id":"https://openalex.org/C89631360","wikidata":"https://www.wikidata.org/wiki/Q1428766","display_name":"Phase noise","level":2,"score":0.21455731987953186},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.13896530866622925},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.09474477171897888}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/icecs49266.2020.9294824","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecs49266.2020.9294824","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.8899999856948853}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":8,"referenced_works":["https://openalex.org/W2057532062","https://openalex.org/W2151755711","https://openalex.org/W2195134145","https://openalex.org/W2516199239","https://openalex.org/W2788680135","https://openalex.org/W2914578411","https://openalex.org/W2971573910","https://openalex.org/W2990281042"],"related_works":["https://openalex.org/W2970351229","https://openalex.org/W2036880312","https://openalex.org/W2129255461","https://openalex.org/W2136555298","https://openalex.org/W2366457522","https://openalex.org/W3140069599","https://openalex.org/W4297360337","https://openalex.org/W2172061050","https://openalex.org/W3174745017","https://openalex.org/W2377134457"],"abstract_inverted_index":{"This":[0],"work":[1],"presents":[2],"a":[3,19,29,35,41,53,59,72,80,107,113],"10":[4],"Bit":[5,43],"digital-to-phase":[6],"converter":[7],"(DPC),":[8],"for":[9,124],"usage":[10],"within":[11],"an":[12],"accurate":[13],"time":[14,131],"synchronization":[15,132],"via":[16,133],"Ethernet":[17,134],"with":[18,52],"nominal":[20,54],"frequency":[21,115],"of":[22,56,66,88],"125":[23],"MHz.":[24],"It":[25],"is":[26,69,97,104],"based":[27,105],"on":[28,106],"16-phase":[30],"ring":[31],"oscillator,":[32],"stabilized":[33],"by":[34,40],"phase-locked":[36],"loop":[37],"(PLL),":[38],"followed":[39],"6":[42],"phase-interpolator":[44],"(PI).":[45],"The":[46],"DPC":[47,68,103],"generates":[48],"1024":[49],"clock":[50],"phases":[51],"resolution":[55],"0.35\u00b0,":[57],"covering":[58],"full":[60],"360\u00b0":[61],"phase":[62],"span.":[63],"A":[64],"prototype":[65],"the":[67,94,102],"fabricated":[70],"in":[71,127],"180":[73],"nm":[74],"technology":[75],"from":[76],"TSMC":[77],"and":[78,82,86,90],"achieves":[79],"differential":[81],"integral":[83],"nonlinearity":[84],"(DNL":[85],"INL)":[87],"0.47\u00b0":[89],"2.33o,":[91],"respectively,":[92],"while":[93],"power":[95],"consumption":[96],"only":[98,112],"4.0":[99],"mW.":[100],"As":[101],"built-in":[108],"PLL,":[109],"it":[110,120],"requires":[111],"low":[114],"reference":[116],"clock,":[117],"which":[118],"makes":[119],"very":[121],"well":[122],"suited":[123],"easy":[125],"integration":[126],"complex":[128],"systems":[129],"(e.g.":[130],"transceivers).":[135]},"counts_by_year":[{"year":2025,"cited_by_count":2}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}