{"id":"https://openalex.org/W3002979870","doi":"https://doi.org/10.1109/icecs46596.2019.8964805","title":"FPGA-based Trigger-Synchronizer for low Frame-Jitter Signal Generation","display_name":"FPGA-based Trigger-Synchronizer for low Frame-Jitter Signal Generation","publication_year":2019,"publication_date":"2019-11-01","ids":{"openalex":"https://openalex.org/W3002979870","doi":"https://doi.org/10.1109/icecs46596.2019.8964805","mag":"3002979870"},"language":"en","primary_location":{"id":"doi:10.1109/icecs46596.2019.8964805","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecs46596.2019.8964805","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 26th IEEE International Conference on Electronics, Circuits and Systems (ICECS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5088690188","display_name":"Dario Russo","orcid":"https://orcid.org/0000-0003-0362-0056"},"institutions":[{"id":"https://openalex.org/I45084792","display_name":"University of Florence","ror":"https://ror.org/04jr1s763","country_code":"IT","type":"education","lineage":["https://openalex.org/I45084792"]}],"countries":["IT"],"is_corresponding":true,"raw_author_name":"Dario Russo","raw_affiliation_strings":["University of Florence,Department of Information Engineering,Florence,Italy","University of Florence, Florence, Italy"],"affiliations":[{"raw_affiliation_string":"University of Florence,Department of Information Engineering,Florence,Italy","institution_ids":["https://openalex.org/I45084792"]},{"raw_affiliation_string":"University of Florence, Florence, Italy","institution_ids":["https://openalex.org/I45084792"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5038935032","display_name":"Stefano Ricci","orcid":"https://orcid.org/0000-0002-7410-6057"},"institutions":[{"id":"https://openalex.org/I45084792","display_name":"University of Florence","ror":"https://ror.org/04jr1s763","country_code":"IT","type":"education","lineage":["https://openalex.org/I45084792"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Stefano Ricci","raw_affiliation_strings":["University of Florence,Department of Information Engineering,Florence,Italy","University of Florence, Florence, Italy"],"affiliations":[{"raw_affiliation_string":"University of Florence,Department of Information Engineering,Florence,Italy","institution_ids":["https://openalex.org/I45084792"]},{"raw_affiliation_string":"University of Florence, Florence, Italy","institution_ids":["https://openalex.org/I45084792"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5088690188"],"corresponding_institution_ids":["https://openalex.org/I45084792"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.15829945,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"406","last_page":"409"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12300","display_name":"Advanced Electrical Measurement Techniques","score":0.9936000108718872,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.9060695171356201},{"id":"https://openalex.org/keywords/signal-edge","display_name":"Signal edge","score":0.8094307780265808},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.6781858205795288},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6348128318786621},{"id":"https://openalex.org/keywords/clock-domain-crossing","display_name":"Clock domain crossing","score":0.6307133436203003},{"id":"https://openalex.org/keywords/synchronizer","display_name":"Synchronizer","score":0.5803631544113159},{"id":"https://openalex.org/keywords/synchronization","display_name":"Synchronization (alternating current)","score":0.5760797262191772},{"id":"https://openalex.org/keywords/signal","display_name":"SIGNAL (programming language)","score":0.5265731811523438},{"id":"https://openalex.org/keywords/waveform","display_name":"Waveform","score":0.5186940431594849},{"id":"https://openalex.org/keywords/clock-skew","display_name":"Clock skew","score":0.49634677171707153},{"id":"https://openalex.org/keywords/digital-clock-manager","display_name":"Digital clock manager","score":0.44655364751815796},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.44328856468200684},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.4279249608516693},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.42613571882247925},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.21711289882659912},{"id":"https://openalex.org/keywords/analog-signal","display_name":"Analog signal","score":0.18210771679878235},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.14399805665016174},{"id":"https://openalex.org/keywords/digital-signal-processing","display_name":"Digital signal processing","score":0.14244845509529114},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.13004902005195618},{"id":"https://openalex.org/keywords/channel","display_name":"Channel (broadcasting)","score":0.0753847062587738}],"concepts":[{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.9060695171356201},{"id":"https://openalex.org/C117525741","wikidata":"https://www.wikidata.org/wiki/Q775654","display_name":"Signal edge","level":4,"score":0.8094307780265808},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.6781858205795288},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6348128318786621},{"id":"https://openalex.org/C127204226","wikidata":"https://www.wikidata.org/wiki/Q5134799","display_name":"Clock domain crossing","level":5,"score":0.6307133436203003},{"id":"https://openalex.org/C66727535","wikidata":"https://www.wikidata.org/wiki/Q7662199","display_name":"Synchronizer","level":2,"score":0.5803631544113159},{"id":"https://openalex.org/C2778562939","wikidata":"https://www.wikidata.org/wiki/Q1298791","display_name":"Synchronization (alternating current)","level":3,"score":0.5760797262191772},{"id":"https://openalex.org/C2779843651","wikidata":"https://www.wikidata.org/wiki/Q7390335","display_name":"SIGNAL (programming language)","level":2,"score":0.5265731811523438},{"id":"https://openalex.org/C197424946","wikidata":"https://www.wikidata.org/wiki/Q1165717","display_name":"Waveform","level":3,"score":0.5186940431594849},{"id":"https://openalex.org/C60501442","wikidata":"https://www.wikidata.org/wiki/Q4382014","display_name":"Clock skew","level":4,"score":0.49634677171707153},{"id":"https://openalex.org/C113074038","wikidata":"https://www.wikidata.org/wiki/Q5276052","display_name":"Digital clock manager","level":5,"score":0.44655364751815796},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.44328856468200684},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.4279249608516693},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.42613571882247925},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.21711289882659912},{"id":"https://openalex.org/C13412647","wikidata":"https://www.wikidata.org/wiki/Q174948","display_name":"Analog signal","level":3,"score":0.18210771679878235},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.14399805665016174},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.14244845509529114},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.13004902005195618},{"id":"https://openalex.org/C127162648","wikidata":"https://www.wikidata.org/wiki/Q16858953","display_name":"Channel (broadcasting)","level":2,"score":0.0753847062587738},{"id":"https://openalex.org/C554190296","wikidata":"https://www.wikidata.org/wiki/Q47528","display_name":"Radar","level":2,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/icecs46596.2019.8964805","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecs46596.2019.8964805","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 26th IEEE International Conference on Electronics, Circuits and Systems (ICECS)","raw_type":"proceedings-article"},{"id":"pmh:oai:flore.unifi.it:2158/1182543","is_oa":false,"landing_page_url":"https://ieeexplore.ieee.org/document/8964805","pdf_url":null,"source":{"id":"https://openalex.org/S4306402033","display_name":"Florence Research (University of Florence)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I45084792","host_organization_name":"University of Florence","host_organization_lineage":["https://openalex.org/I45084792"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"info:eu-repo/semantics/conferenceObject"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.5899999737739563,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":9,"referenced_works":["https://openalex.org/W1975326636","https://openalex.org/W2096130935","https://openalex.org/W2156435621","https://openalex.org/W2164964876","https://openalex.org/W2564226817","https://openalex.org/W2773000235","https://openalex.org/W2889420974","https://openalex.org/W2946577045","https://openalex.org/W6910313054"],"related_works":["https://openalex.org/W2096393085","https://openalex.org/W2569163161","https://openalex.org/W1995174288","https://openalex.org/W2107880456","https://openalex.org/W2161776375","https://openalex.org/W2071461855","https://openalex.org/W2988028249","https://openalex.org/W2097148648","https://openalex.org/W3002979870","https://openalex.org/W2391100687"],"abstract_inverted_index":{"Commercial":[0],"waveform":[1],"function":[2],"generators":[3,67],"can":[4,102],"be":[5,103],"set":[6],"to":[7,83,88],"produce":[8],"signal":[9,149],"bursts":[10,150],"that":[11,80,140],"start":[12],"when":[13,141],"a":[14,38,92,110,129,134],"trigger":[15,23,93,101,119],"pulse":[16,24,106],"is":[17,30,35,78,81,145,158],"applied.":[18],"Unfortunately,":[19],"the":[20,26,41,60,63,66,69,89,100,115,118,126,142,156],"delay":[21],"between":[22,117],"and":[25,121,131],"effective":[27],"burst":[28],"generation":[29],"not":[31,108],"constant,":[32],"but":[33],"it":[34],"affected":[36],"by":[37,125,152],"jitter":[39,57],"in":[40,68],"order":[42],"of":[43,46,65,91,128],"some":[44],"hundreds":[45],"ps":[47,161],"or":[48],"more.":[49],"In":[50,71],"sensitive":[51],"applications,":[52],"like":[53],"ultrasound":[54],"Doppler,":[55],"this":[56,72],"affects":[58],"negatively":[59],"measurements,":[61],"limiting":[62],"use":[64],"experiments.":[70],"paper,":[73],"an":[74,85,104,153],"FPGA":[75],"re-synchronization":[76,98],"circuit":[77,113,144],"presented":[79],"able":[82],"re-phase":[84,132],"internal":[86,123,136],"clock":[87,124],"edge":[90,120],"pulse.":[94],"Unlike":[95],"other":[96],"commercial":[97],"devices,":[99],"arbitrary":[105],"sequence,":[107],"necessarily":[109],"clock.":[111,137],"The":[112],"measures":[114],"phase":[116],"its":[122],"means":[127],"Tapped-Delay-Line,":[130],"accordingly":[133],"second":[135],"Experiments":[138],"show":[139],"proposed":[143],"used":[146],"for":[147],"generating":[148],"triggered":[151],"external":[154],"signal,":[155],"frame-jitter":[157],"below":[159],"100":[160],"rms.":[162]},"counts_by_year":[{"year":2023,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}