{"id":"https://openalex.org/W3001481144","doi":"https://doi.org/10.1109/icecs46596.2019.8964789","title":"Fully-Synthesizable Current-Input ADCs for Ultra-Low Area and Minimal Design Effort","display_name":"Fully-Synthesizable Current-Input ADCs for Ultra-Low Area and Minimal Design Effort","publication_year":2019,"publication_date":"2019-11-01","ids":{"openalex":"https://openalex.org/W3001481144","doi":"https://doi.org/10.1109/icecs46596.2019.8964789","mag":"3001481144"},"language":"en","primary_location":{"id":"doi:10.1109/icecs46596.2019.8964789","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecs46596.2019.8964789","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 26th IEEE International Conference on Electronics, Circuits and Systems (ICECS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"https://scholarbank.nus.edu.sg/handle/10635/189170","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5068038161","display_name":"Orazio Aiello","orcid":"https://orcid.org/0000-0002-6938-9806"},"institutions":[{"id":"https://openalex.org/I165932596","display_name":"National University of Singapore","ror":"https://ror.org/01tgyzw49","country_code":"SG","type":"education","lineage":["https://openalex.org/I165932596"]}],"countries":["SG"],"is_corresponding":true,"raw_author_name":"Orazio Aiello","raw_affiliation_strings":["National Univ. of Singapore,ECE,Singapore","ECE, National Univ. of Singapore, Singapore"],"affiliations":[{"raw_affiliation_string":"National Univ. of Singapore,ECE,Singapore","institution_ids":["https://openalex.org/I165932596"]},{"raw_affiliation_string":"ECE, National Univ. of Singapore, Singapore","institution_ids":["https://openalex.org/I165932596"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5048892532","display_name":"Paolo Crovetti","orcid":"https://orcid.org/0000-0002-2484-1686"},"institutions":[{"id":"https://openalex.org/I177477856","display_name":"Polytechnic University of Turin","ror":"https://ror.org/00bgk9508","country_code":"IT","type":"education","lineage":["https://openalex.org/I177477856"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Paolo Crovetti","raw_affiliation_strings":["Politecnico di Torino,DET,Torino,Italy","Politecnico di Torino, Torino, Italy"],"affiliations":[{"raw_affiliation_string":"Politecnico di Torino,DET,Torino,Italy","institution_ids":["https://openalex.org/I177477856"]},{"raw_affiliation_string":"Politecnico di Torino, Torino, Italy","institution_ids":["https://openalex.org/I177477856"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101029752","display_name":"Ayushparth Sharma","orcid":null},"institutions":[{"id":"https://openalex.org/I165932596","display_name":"National University of Singapore","ror":"https://ror.org/01tgyzw49","country_code":"SG","type":"education","lineage":["https://openalex.org/I165932596"]}],"countries":["SG"],"is_corresponding":false,"raw_author_name":"Ayushparth Sharma","raw_affiliation_strings":["National Univ. of Singapore,ECE,Singapore","ECE, National Univ. of Singapore, Singapore"],"affiliations":[{"raw_affiliation_string":"National Univ. of Singapore,ECE,Singapore","institution_ids":["https://openalex.org/I165932596"]},{"raw_affiliation_string":"ECE, National Univ. of Singapore, Singapore","institution_ids":["https://openalex.org/I165932596"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5052037141","display_name":"Massimo Alioto","orcid":"https://orcid.org/0000-0002-4127-8258"},"institutions":[{"id":"https://openalex.org/I165932596","display_name":"National University of Singapore","ror":"https://ror.org/01tgyzw49","country_code":"SG","type":"education","lineage":["https://openalex.org/I165932596"]}],"countries":["SG"],"is_corresponding":false,"raw_author_name":"Massimo Alioto","raw_affiliation_strings":["National Univ. of Singapore,ECE,Singapore","ECE, National Univ. of Singapore, Singapore"],"affiliations":[{"raw_affiliation_string":"National Univ. of Singapore,ECE,Singapore","institution_ids":["https://openalex.org/I165932596"]},{"raw_affiliation_string":"ECE, National Univ. of Singapore, Singapore","institution_ids":["https://openalex.org/I165932596"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5068038161"],"corresponding_institution_ids":["https://openalex.org/I165932596"],"apc_list":null,"apc_paid":null,"fwci":0.3912,"has_fulltext":false,"cited_by_count":7,"citation_normalized_percentile":{"value":0.60338272,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"715","last_page":"718"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11992","display_name":"CCD and CMOS Imaging Sensors","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/software-portability","display_name":"Software portability","score":0.6825032234191895},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6727838516235352},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.663040041923523},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.5872333645820618},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.47300392389297485},{"id":"https://openalex.org/keywords/integrated-circuit-design","display_name":"Integrated circuit design","score":0.4634402096271515},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4245983958244324},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.40185171365737915},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.32536646723747253},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.29770058393478394},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.14834818243980408},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.13283884525299072}],"concepts":[{"id":"https://openalex.org/C63000827","wikidata":"https://www.wikidata.org/wiki/Q3080428","display_name":"Software portability","level":2,"score":0.6825032234191895},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6727838516235352},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.663040041923523},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.5872333645820618},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.47300392389297485},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.4634402096271515},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4245983958244324},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.40185171365737915},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.32536646723747253},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.29770058393478394},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.14834818243980408},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.13283884525299072},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1109/icecs46596.2019.8964789","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecs46596.2019.8964789","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 26th IEEE International Conference on Electronics, Circuits and Systems (ICECS)","raw_type":"proceedings-article"},{"id":"pmh:oai:scholarbank.nus.edu.sg:10635/189170","is_oa":true,"landing_page_url":"https://scholarbank.nus.edu.sg/handle/10635/189170","pdf_url":null,"source":{"id":"https://openalex.org/S7407052290","display_name":"National University of Singapore","issn_l":null,"issn":[],"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":"public-domain","license_id":"https://openalex.org/licenses/public-domain","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"Article"},{"id":"pmh:oai:iris.unige.it:11567/1097214","is_oa":false,"landing_page_url":"https://hdl.handle.net/11567/1097214","pdf_url":null,"source":{"id":"https://openalex.org/S4377196291","display_name":"CINECA IRIS Institutial Research Information System (University of Genoa)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I83816512","host_organization_name":"University of Genoa","host_organization_lineage":["https://openalex.org/I83816512"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"info:eu-repo/semantics/conferenceObject"}],"best_oa_location":{"id":"pmh:oai:scholarbank.nus.edu.sg:10635/189170","is_oa":true,"landing_page_url":"https://scholarbank.nus.edu.sg/handle/10635/189170","pdf_url":null,"source":{"id":"https://openalex.org/S7407052290","display_name":"National University of Singapore","issn_l":null,"issn":[],"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":"public-domain","license_id":"https://openalex.org/licenses/public-domain","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"Article"},"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9","score":0.6100000143051147}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":19,"referenced_works":["https://openalex.org/W1969925016","https://openalex.org/W1981151840","https://openalex.org/W1983740965","https://openalex.org/W1995306443","https://openalex.org/W2075322541","https://openalex.org/W2114450751","https://openalex.org/W2161321446","https://openalex.org/W2242139250","https://openalex.org/W2540707026","https://openalex.org/W2566998670","https://openalex.org/W2580425382","https://openalex.org/W2609793316","https://openalex.org/W2795591835","https://openalex.org/W2886464697","https://openalex.org/W2891288687","https://openalex.org/W2918220617","https://openalex.org/W2928458286","https://openalex.org/W2943848730","https://openalex.org/W2970430020"],"related_works":["https://openalex.org/W4253195573","https://openalex.org/W2020934033","https://openalex.org/W3147061323","https://openalex.org/W63276784","https://openalex.org/W3011978806","https://openalex.org/W2156446048","https://openalex.org/W2059530328","https://openalex.org/W2098419840","https://openalex.org/W2118796996","https://openalex.org/W4235353373"],"abstract_inverted_index":{"A":[0,75],"fully":[1],"synthesizable":[2],"ADC":[3,25],"architecture":[4],"is":[5,103],"proposed":[6,24],"for":[7,131],"low-end":[8],"current":[9,61],"sensing":[10],"applications.":[11],"Being":[12],"based":[13],"on":[14],"standard":[15],"cells":[16],"and":[17,37,43,80,87,142,148],"designed":[18,141],"with":[19,113,144],"a":[20,65,71,108,132,150],"fully-automated":[21],"flow,":[22],"the":[23,95,98,104,114,117,121,129,154],"allows":[26,59],"very":[27],"low":[28,48],"area,":[29],"digital-like":[30],"scaling":[31],"across":[32],"CMOS":[33],"technology":[34,36],"generations,":[35],"design":[38,41,46],"portability,":[39],"minimal":[40],"effort,":[42],"immersed-in":[44],"logic":[45,145],"(i.e.,":[47],"integration":[49],"effort),":[50],"compared":[51],"to":[52,73,127],"traditional":[53],"analog-intensive":[54],"designs.":[55],"In":[56],"addition,":[57],"it":[58],"direct":[60],"readout":[62],"without":[63],"requiring":[64],"transresistance":[66],"stage.":[67],"Testchip":[68],"measurements":[69],"show":[70],"5-nA":[72],"1-\u03bc":[74],"input":[76],"range,":[77],"6.7-bit":[78],"ENOB":[79],"2.2-kS/s":[81],"sample":[82],"rate,":[83],"at":[84],"940-nW":[85],"power":[86],"4,580-\u03bc":[88],"m":[89],"<sup":[90],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[91],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">2</sup>":[92],"area.":[93],"To":[94],"best":[96],"of":[97,107,116,120,135,156],"authors'":[99],"knowledge,":[100],"this":[101,124],"testchip":[102],"first":[105],"demonstration":[106],"fully-synthesizable":[109],"input-current":[110],"ADC.":[111],"Along":[112],"analysis":[115],"specific":[118],"limitations":[119],"presented":[122],"demonstration,":[123],"work":[125],"aims":[126],"pave":[128],"way":[130],"new":[133],"class":[134],"current-input":[136],"ADCs":[137],"that":[138],"can":[139],"be":[140],"integrated":[143],"within":[146],"hours,":[147],"occupy":[149],"silicon":[151],"area":[152],"in":[153],"order":[155],"10kgates.":[157]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":2},{"year":2022,"cited_by_count":2},{"year":2021,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
