{"id":"https://openalex.org/W4311224407","doi":"https://doi.org/10.1109/icecs202256217.2022.9970947","title":"Investigation of Pass Transistor Logic in a 12nm FinFET CMOS Technology","display_name":"Investigation of Pass Transistor Logic in a 12nm FinFET CMOS Technology","publication_year":2022,"publication_date":"2022-10-24","ids":{"openalex":"https://openalex.org/W4311224407","doi":"https://doi.org/10.1109/icecs202256217.2022.9970947"},"language":"en","primary_location":{"id":"doi:10.1109/icecs202256217.2022.9970947","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecs202256217.2022.9970947","pdf_url":null,"source":{"id":"https://openalex.org/S4363607963","display_name":"2022 29th IEEE International Conference on Electronics, Circuits and Systems (ICECS)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2022 29th IEEE International Conference on Electronics, Circuits and Systems (ICECS)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5073539369","display_name":"Andr\u00e9 Lucas Chinazzo","orcid":null},"institutions":[{"id":"https://openalex.org/I153267046","display_name":"University of Kaiserslautern","ror":"https://ror.org/04zrf7b53","country_code":"DE","type":"education","lineage":["https://openalex.org/I153267046"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Andre L. Chinazzo","raw_affiliation_strings":["Technische Universität Kaiserslautern,Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Technische Universität Kaiserslautern,Germany","institution_ids":["https://openalex.org/I153267046"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5073743729","display_name":"Jan Lappas","orcid":null},"institutions":[{"id":"https://openalex.org/I153267046","display_name":"University of Kaiserslautern","ror":"https://ror.org/04zrf7b53","country_code":"DE","type":"education","lineage":["https://openalex.org/I153267046"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Jan Lappas","raw_affiliation_strings":["Technische Universität Kaiserslautern,Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Technische Universität Kaiserslautern,Germany","institution_ids":["https://openalex.org/I153267046"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5090870819","display_name":"Christian Weis","orcid":"https://orcid.org/0000-0002-4152-0200"},"institutions":[{"id":"https://openalex.org/I153267046","display_name":"University of Kaiserslautern","ror":"https://ror.org/04zrf7b53","country_code":"DE","type":"education","lineage":["https://openalex.org/I153267046"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Christian Weis","raw_affiliation_strings":["Technische Universität Kaiserslautern,Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Technische Universität Kaiserslautern,Germany","institution_ids":["https://openalex.org/I153267046"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5044827128","display_name":"Qinhui Huang","orcid":"https://orcid.org/0000-0001-7086-8655"},"institutions":[{"id":"https://openalex.org/I2250955327","display_name":"Huawei Technologies (China)","ror":"https://ror.org/00cmhce21","country_code":"CN","type":"company","lineage":["https://openalex.org/I2250955327"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Qinhui Huang","raw_affiliation_strings":["Huawei Technologies Co., Ltd.,Shenzhen,China","Huawei Technologies Co., Ltd., Shenzhen, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Huawei Technologies Co., Ltd.,Shenzhen,China","institution_ids":["https://openalex.org/I2250955327"]},{"raw_affiliation_string":"Huawei Technologies Co., Ltd., Shenzhen, China","institution_ids":["https://openalex.org/I2250955327"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5042493542","display_name":"Zhihang Wu","orcid":"https://orcid.org/0000-0002-1948-4848"},"institutions":[{"id":"https://openalex.org/I2250955327","display_name":"Huawei Technologies (China)","ror":"https://ror.org/00cmhce21","country_code":"CN","type":"company","lineage":["https://openalex.org/I2250955327"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Zhihang Wu","raw_affiliation_strings":["Huawei Technologies Co., Ltd.,Shenzhen,China","Huawei Technologies Co., Ltd., Shenzhen, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Huawei Technologies Co., Ltd.,Shenzhen,China","institution_ids":["https://openalex.org/I2250955327"]},{"raw_affiliation_string":"Huawei Technologies Co., Ltd., Shenzhen, China","institution_ids":["https://openalex.org/I2250955327"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5030240223","display_name":"Leibin Ni","orcid":"https://orcid.org/0000-0002-5480-3146"},"institutions":[{"id":"https://openalex.org/I2250955327","display_name":"Huawei Technologies (China)","ror":"https://ror.org/00cmhce21","country_code":"CN","type":"company","lineage":["https://openalex.org/I2250955327"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Leibin Ni","raw_affiliation_strings":["Huawei Technologies Co., Ltd.,Shenzhen,China","Huawei Technologies Co., Ltd., Shenzhen, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Huawei Technologies Co., Ltd.,Shenzhen,China","institution_ids":["https://openalex.org/I2250955327"]},{"raw_affiliation_string":"Huawei Technologies Co., Ltd., Shenzhen, China","institution_ids":["https://openalex.org/I2250955327"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5059285190","display_name":"Norbert Wehn","orcid":"https://orcid.org/0000-0002-9010-086X"},"institutions":[{"id":"https://openalex.org/I153267046","display_name":"University of Kaiserslautern","ror":"https://ror.org/04zrf7b53","country_code":"DE","type":"education","lineage":["https://openalex.org/I153267046"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Norbert Wehn","raw_affiliation_strings":["Technische Universität Kaiserslautern,Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Technische Universität Kaiserslautern,Germany","institution_ids":["https://openalex.org/I153267046"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.652,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.82996899,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":91,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.8705376386642456},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.7982397675514221},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.6117553114891052},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.608974039554596},{"id":"https://openalex.org/keywords/pass-transistor-logic","display_name":"Pass transistor logic","score":0.5963518619537354},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5871399641036987},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.5048497319221497},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.5023057460784912},{"id":"https://openalex.org/keywords/power\u2013delay-product","display_name":"Power\u2013delay product","score":0.4524655342102051},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.4412151873111725},{"id":"https://openalex.org/keywords/nmos-logic","display_name":"NMOS logic","score":0.4210744798183441},{"id":"https://openalex.org/keywords/integrated-injection-logic","display_name":"Integrated injection logic","score":0.41295015811920166},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.4053671360015869},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.3736416697502136},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.3287815451622009},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2915073037147522},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.25064438581466675}],"concepts":[{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.8705376386642456},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.7982397675514221},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.6117553114891052},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.608974039554596},{"id":"https://openalex.org/C198521697","wikidata":"https://www.wikidata.org/wiki/Q7142438","display_name":"Pass transistor logic","level":4,"score":0.5963518619537354},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5871399641036987},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.5048497319221497},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.5023057460784912},{"id":"https://openalex.org/C2776391166","wikidata":"https://www.wikidata.org/wiki/Q7236873","display_name":"Power\u2013delay product","level":4,"score":0.4524655342102051},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.4412151873111725},{"id":"https://openalex.org/C197162436","wikidata":"https://www.wikidata.org/wiki/Q83908","display_name":"NMOS logic","level":4,"score":0.4210744798183441},{"id":"https://openalex.org/C159903706","wikidata":"https://www.wikidata.org/wiki/Q173574","display_name":"Integrated injection logic","level":5,"score":0.41295015811920166},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.4053671360015869},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.3736416697502136},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.3287815451622009},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2915073037147522},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.25064438581466675}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/icecs202256217.2022.9970947","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecs202256217.2022.9970947","pdf_url":null,"source":{"id":"https://openalex.org/S4363607963","display_name":"2022 29th IEEE International Conference on Electronics, Circuits and Systems (ICECS)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2022 29th IEEE International Conference on Electronics, Circuits and Systems (ICECS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.5099999904632568,"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W14468352","https://openalex.org/W2119985366","https://openalex.org/W2141849037","https://openalex.org/W2157555699","https://openalex.org/W2314747031","https://openalex.org/W2803057706","https://openalex.org/W3134526034","https://openalex.org/W3162163331","https://openalex.org/W3163556913","https://openalex.org/W4280589410","https://openalex.org/W6677814527","https://openalex.org/W6698929447"],"related_works":["https://openalex.org/W2186697267","https://openalex.org/W2168324060","https://openalex.org/W1485027372","https://openalex.org/W2017528947","https://openalex.org/W1843096359","https://openalex.org/W4206656053","https://openalex.org/W1900707063","https://openalex.org/W2155174752","https://openalex.org/W2112242076","https://openalex.org/W4242766712"],"abstract_inverted_index":{"For":[0,104],"the":[1,11,38,174,184,214],"past":[2],"two":[3],"decades,":[4],"complementary":[5,75,128,215],"static":[6,76,129],"CMOS":[7,77,130,180,216],"logic":[8,14,78,131,217],"has":[9,33],"been":[10],"dominant":[12],"digital":[13],"style":[15],"because":[16],"of":[17,102,122,161,204,231],"its":[18,54,72],"robustness":[19],"and":[20,53,65,70,92,200,209,242],"efficient":[21],"deployment":[22],"in":[23,37,48,56,79,167],"standard":[24,145,162],"cell":[25,146],"based":[26,117,218],"design":[27,251],"flows.":[28],"Pass":[29],"Transistor":[30],"Logic":[31],"(PTL)":[32],"attracted":[34],"much":[35],"attention":[36],"'90s;":[39],"however,":[40],"there":[41],"are":[42,97,141,148,177],"hardly":[43],"any":[44],"investigations":[45],"for":[46,233,238,244],"PTL":[47,69,124,165,175],"advanced":[49,81],"commercial":[50,82,144],"technology":[51],"nodes":[52],"use":[55],"larger":[57,168],"circuits.":[58],"In":[59,171],"this":[60,105],"paper,":[61],"we":[62,107,221],"investigate":[63],"adders":[64,163,166,194],"multipliers":[66],"circuits":[67],"using":[68,133],"demonstrate":[71,222],"advantages":[73],"over":[74],"an":[80,119],"FinFET":[83,137],"technology.":[84,138],"Special":[85],"focus":[86],"is":[87],"put":[88],"on":[89,118],"process,":[90],"voltage,":[91],"temperature":[93],"(PVT)":[94],"variations":[95],"that":[96,140,191,223],"considered":[98],"as":[99],"large":[100],"disadvantages":[101],"PTL.":[103],"purpose,":[106],"select":[108],"three":[109],"most":[110],"promising":[111],"PTL-based":[112,192],"1-bit":[113,193],"Full":[114],"Adders":[115],"(FA)":[116],"in-depth":[120],"comparison":[121],"22":[123],"FAs":[125],"to":[126,182,206,213],"a":[127,134,228,234,249],"reference":[132],"recent":[135],"12nm":[136],"Layouts":[139],"compatible":[142],"with":[143,179],"libraries":[147],"implemented,":[149],"hence":[150],"all":[151],"our":[152,172,224],"results":[153],"include":[154],"extracted":[155],"parasitics.":[156],"We":[157],"explore":[158],"replacement":[159,225],"strategies":[160],"by":[164,248],"building":[169],"blocks.":[170],"designs,":[173],"cells":[176,181],"interleaved":[178],"reduce":[183],"circuit":[185],"PVT":[186],"sensitivity.":[187],"Our":[188],"investigation":[189],"shows":[190],"achieve":[195],"delay,":[196],"average":[197],"dynamic":[198],"power,":[199],"Power-Delay-Product":[201],"(PDP)":[202],"reductions":[203],"up":[205],"72.9%,":[207],"45.7%,":[208],"78.5%,":[210],"respectively,":[211],"compared":[212],"adder.":[219],"Further,":[220],"strategy":[226],"yields":[227],"PDP":[229],"reduction":[230],"39.6%":[232],"32-bit":[235],"ripple-carry-adder,":[236],"22.6%":[237],"the$6\\times":[239],"6$Baugh-Wooley":[240],"multiplier,":[241],"21%":[243],"an$8\\times":[245],"8$multiplier":[246],"optimized":[247],"state-of-the-art":[250],"flow.":[252]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":3}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}