{"id":"https://openalex.org/W4311277328","doi":"https://doi.org/10.1109/icecs202256217.2022.9970886","title":"High-throughput FFT architectures using HLS tools","display_name":"High-throughput FFT architectures using HLS tools","publication_year":2022,"publication_date":"2022-10-24","ids":{"openalex":"https://openalex.org/W4311277328","doi":"https://doi.org/10.1109/icecs202256217.2022.9970886"},"language":"en","primary_location":{"id":"doi:10.1109/icecs202256217.2022.9970886","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecs202256217.2022.9970886","pdf_url":null,"source":{"id":"https://openalex.org/S4363607963","display_name":"2022 29th IEEE International Conference on Electronics, Circuits and Systems (ICECS)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2022 29th IEEE International Conference on Electronics, Circuits and Systems (ICECS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5078888977","display_name":"Hugues Almorin","orcid":null},"institutions":[{"id":"https://openalex.org/I1294671590","display_name":"Centre National de la Recherche Scientifique","ror":"https://ror.org/02feahw73","country_code":"FR","type":"government","lineage":["https://openalex.org/I1294671590"]},{"id":"https://openalex.org/I15057530","display_name":"Universit\u00e9 de Bordeaux","ror":"https://ror.org/057qpr032","country_code":"FR","type":"education","lineage":["https://openalex.org/I15057530"]},{"id":"https://openalex.org/I4210157089","display_name":"Laboratoire de l'Int\u00e9gration du Mat\u00e9riau au Syst\u00e8me","ror":"https://ror.org/04nabhy78","country_code":"FR","type":"facility","lineage":["https://openalex.org/I1294671590","https://openalex.org/I1294671590","https://openalex.org/I15057530","https://openalex.org/I4210091158","https://openalex.org/I4210095849","https://openalex.org/I4210157089","https://openalex.org/I4210160189"]},{"id":"https://openalex.org/I4210160189","display_name":"Institut Polytechnique de Bordeaux","ror":"https://ror.org/054qv7y42","country_code":"FR","type":"education","lineage":["https://openalex.org/I4210160189"]}],"countries":["FR"],"is_corresponding":true,"raw_author_name":"Hugues Almorin","raw_affiliation_strings":["Bordeaux-INP, Univ. of Bordeaux,IMS Laboratory (CNRS UMR 5218),France"],"affiliations":[{"raw_affiliation_string":"Bordeaux-INP, Univ. of Bordeaux,IMS Laboratory (CNRS UMR 5218),France","institution_ids":["https://openalex.org/I4210157089","https://openalex.org/I4210160189","https://openalex.org/I1294671590","https://openalex.org/I15057530"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5079950326","display_name":"Bertrand Le Gal","orcid":"https://orcid.org/0000-0003-2269-8756"},"institutions":[{"id":"https://openalex.org/I1294671590","display_name":"Centre National de la Recherche Scientifique","ror":"https://ror.org/02feahw73","country_code":"FR","type":"government","lineage":["https://openalex.org/I1294671590"]},{"id":"https://openalex.org/I15057530","display_name":"Universit\u00e9 de Bordeaux","ror":"https://ror.org/057qpr032","country_code":"FR","type":"education","lineage":["https://openalex.org/I15057530"]},{"id":"https://openalex.org/I4210157089","display_name":"Laboratoire de l'Int\u00e9gration du Mat\u00e9riau au Syst\u00e8me","ror":"https://ror.org/04nabhy78","country_code":"FR","type":"facility","lineage":["https://openalex.org/I1294671590","https://openalex.org/I1294671590","https://openalex.org/I15057530","https://openalex.org/I4210091158","https://openalex.org/I4210095849","https://openalex.org/I4210157089","https://openalex.org/I4210160189"]},{"id":"https://openalex.org/I4210160189","display_name":"Institut Polytechnique de Bordeaux","ror":"https://ror.org/054qv7y42","country_code":"FR","type":"education","lineage":["https://openalex.org/I4210160189"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Bertrand Le Gal","raw_affiliation_strings":["Bordeaux-INP, Univ. of Bordeaux,IMS Laboratory (CNRS UMR 5218),France"],"affiliations":[{"raw_affiliation_string":"Bordeaux-INP, Univ. of Bordeaux,IMS Laboratory (CNRS UMR 5218),France","institution_ids":["https://openalex.org/I4210157089","https://openalex.org/I4210160189","https://openalex.org/I1294671590","https://openalex.org/I15057530"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5054787159","display_name":"J\u00e9r\u00e9mie Crenne","orcid":null},"institutions":[{"id":"https://openalex.org/I1294671590","display_name":"Centre National de la Recherche Scientifique","ror":"https://ror.org/02feahw73","country_code":"FR","type":"government","lineage":["https://openalex.org/I1294671590"]},{"id":"https://openalex.org/I15057530","display_name":"Universit\u00e9 de Bordeaux","ror":"https://ror.org/057qpr032","country_code":"FR","type":"education","lineage":["https://openalex.org/I15057530"]},{"id":"https://openalex.org/I4210157089","display_name":"Laboratoire de l'Int\u00e9gration du Mat\u00e9riau au Syst\u00e8me","ror":"https://ror.org/04nabhy78","country_code":"FR","type":"facility","lineage":["https://openalex.org/I1294671590","https://openalex.org/I1294671590","https://openalex.org/I15057530","https://openalex.org/I4210091158","https://openalex.org/I4210095849","https://openalex.org/I4210157089","https://openalex.org/I4210160189"]},{"id":"https://openalex.org/I4210160189","display_name":"Institut Polytechnique de Bordeaux","ror":"https://ror.org/054qv7y42","country_code":"FR","type":"education","lineage":["https://openalex.org/I4210160189"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Jeremie Crenne","raw_affiliation_strings":["Bordeaux-INP, Univ. of Bordeaux,IMS Laboratory (CNRS UMR 5218),France"],"affiliations":[{"raw_affiliation_string":"Bordeaux-INP, Univ. of Bordeaux,IMS Laboratory (CNRS UMR 5218),France","institution_ids":["https://openalex.org/I4210157089","https://openalex.org/I4210160189","https://openalex.org/I1294671590","https://openalex.org/I15057530"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5031142198","display_name":"Christophe J\u00e9go","orcid":"https://orcid.org/0000-0001-5964-6277"},"institutions":[{"id":"https://openalex.org/I1294671590","display_name":"Centre National de la Recherche Scientifique","ror":"https://ror.org/02feahw73","country_code":"FR","type":"government","lineage":["https://openalex.org/I1294671590"]},{"id":"https://openalex.org/I15057530","display_name":"Universit\u00e9 de Bordeaux","ror":"https://ror.org/057qpr032","country_code":"FR","type":"education","lineage":["https://openalex.org/I15057530"]},{"id":"https://openalex.org/I4210157089","display_name":"Laboratoire de l'Int\u00e9gration du Mat\u00e9riau au Syst\u00e8me","ror":"https://ror.org/04nabhy78","country_code":"FR","type":"facility","lineage":["https://openalex.org/I1294671590","https://openalex.org/I1294671590","https://openalex.org/I15057530","https://openalex.org/I4210091158","https://openalex.org/I4210095849","https://openalex.org/I4210157089","https://openalex.org/I4210160189"]},{"id":"https://openalex.org/I4210160189","display_name":"Institut Polytechnique de Bordeaux","ror":"https://ror.org/054qv7y42","country_code":"FR","type":"education","lineage":["https://openalex.org/I4210160189"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Christophe Jego","raw_affiliation_strings":["Bordeaux-INP, Univ. of Bordeaux,IMS Laboratory (CNRS UMR 5218),France"],"affiliations":[{"raw_affiliation_string":"Bordeaux-INP, Univ. of Bordeaux,IMS Laboratory (CNRS UMR 5218),France","institution_ids":["https://openalex.org/I4210157089","https://openalex.org/I4210160189","https://openalex.org/I1294671590","https://openalex.org/I15057530"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5057954458","display_name":"Vincent Kissel","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Vincent Kissel","raw_affiliation_strings":["ARELIS (LGM Group),Saint-Aubin-l&#x00E8;s-Elbeuf,France"],"affiliations":[{"raw_affiliation_string":"ARELIS (LGM Group),Saint-Aubin-l&#x00E8;s-Elbeuf,France","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5078888977"],"corresponding_institution_ids":["https://openalex.org/I1294671590","https://openalex.org/I15057530","https://openalex.org/I4210157089","https://openalex.org/I4210160189"],"apc_list":null,"apc_paid":null,"fwci":1.2868,"has_fulltext":false,"cited_by_count":6,"citation_normalized_percentile":{"value":0.78361982,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":91,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9961000084877014,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/fast-fourier-transform","display_name":"Fast Fourier transform","score":0.8093596696853638},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.772553563117981},{"id":"https://openalex.org/keywords/design-space-exploration","display_name":"Design space exploration","score":0.7308865785598755},{"id":"https://openalex.org/keywords/throughput","display_name":"Throughput","score":0.6712077260017395},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.6422164440155029},{"id":"https://openalex.org/keywords/usable","display_name":"USable","score":0.6016258001327515},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5805269479751587},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.5382257699966431},{"id":"https://openalex.org/keywords/digital-signal-processing","display_name":"Digital signal processing","score":0.4849112629890442},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.479155957698822},{"id":"https://openalex.org/keywords/signal-processing","display_name":"Signal processing","score":0.43202126026153564},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.3758147656917572},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.34715035557746887},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.21741995215415955},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.19092947244644165}],"concepts":[{"id":"https://openalex.org/C75172450","wikidata":"https://www.wikidata.org/wiki/Q623950","display_name":"Fast Fourier transform","level":2,"score":0.8093596696853638},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.772553563117981},{"id":"https://openalex.org/C2776221188","wikidata":"https://www.wikidata.org/wiki/Q21072556","display_name":"Design space exploration","level":2,"score":0.7308865785598755},{"id":"https://openalex.org/C157764524","wikidata":"https://www.wikidata.org/wiki/Q1383412","display_name":"Throughput","level":3,"score":0.6712077260017395},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.6422164440155029},{"id":"https://openalex.org/C2780615836","wikidata":"https://www.wikidata.org/wiki/Q2471869","display_name":"USable","level":2,"score":0.6016258001327515},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5805269479751587},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.5382257699966431},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.4849112629890442},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.479155957698822},{"id":"https://openalex.org/C104267543","wikidata":"https://www.wikidata.org/wiki/Q208163","display_name":"Signal processing","level":3,"score":0.43202126026153564},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3758147656917572},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.34715035557746887},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.21741995215415955},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.19092947244644165},{"id":"https://openalex.org/C136764020","wikidata":"https://www.wikidata.org/wiki/Q466","display_name":"World Wide Web","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C555944384","wikidata":"https://www.wikidata.org/wiki/Q249","display_name":"Wireless","level":2,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/icecs202256217.2022.9970886","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecs202256217.2022.9970886","pdf_url":null,"source":{"id":"https://openalex.org/S4363607963","display_name":"2022 29th IEEE International Conference on Electronics, Circuits and Systems (ICECS)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2022 29th IEEE International Conference on Electronics, Circuits and Systems (ICECS)","raw_type":"proceedings-article"},{"id":"pmh:oai:HAL:hal-04158201v1","is_oa":false,"landing_page_url":"https://hal.science/hal-04158201","pdf_url":null,"source":{"id":"https://openalex.org/S4406922461","display_name":"SPIRE - Sciences Po Institutional REpository","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"2022 29th IEEE International Conference on Electronics, Circuits and Systems (ICECS), Oct 2022, Glasgow, United Kingdom. pp.1-4, &#x27E8;10.1109/ICECS202256217.2022.9970886&#x27E9;","raw_type":"Conference papers"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.4300000071525574,"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":17,"referenced_works":["https://openalex.org/W2025265972","https://openalex.org/W2065743933","https://openalex.org/W2090040267","https://openalex.org/W2102182691","https://openalex.org/W2188205002","https://openalex.org/W2253587711","https://openalex.org/W2337452330","https://openalex.org/W2685631283","https://openalex.org/W2763092413","https://openalex.org/W2909122534","https://openalex.org/W2943140017","https://openalex.org/W3006155189","https://openalex.org/W3010781441","https://openalex.org/W3026871068","https://openalex.org/W4297780740","https://openalex.org/W6687345011","https://openalex.org/W6751092147"],"related_works":["https://openalex.org/W4281926497","https://openalex.org/W2274562545","https://openalex.org/W2269990635","https://openalex.org/W3146054601","https://openalex.org/W1978911128","https://openalex.org/W2042762783","https://openalex.org/W4283730710","https://openalex.org/W4313484792","https://openalex.org/W2921149022","https://openalex.org/W4281784598"],"abstract_inverted_index":{"High-Level":[0],"Synthesis":[1],"(HLS)":[2],"tools":[3,52,72],"are":[4,53],"an":[5],"attractive":[6],"option":[7],"for":[8],"fast":[9],"prototyping":[10],"and":[11,31],"implementation":[12],"of":[13,35,88,93],"hardware":[14],"accelerators":[15],"performing":[16],"digital":[17],"signal":[18],"processing":[19],"algorithms":[20],"such":[21],"as":[22,109],"the":[23,29,32,36,41,56],"Fast":[24],"Fourier":[25],"Transform":[26],"(FFT).":[27],"However,":[28],"efficiency":[30],"performance":[33],"level":[34],"generated":[37],"architectures":[38,103],"depend":[39],"on":[40],"behavioral":[42,57,67],"models.":[43],"Moreover,":[44],"Design":[45],"Space":[46],"Exploration":[47],"features":[48],"enabled":[49],"by":[50,55,85,111],"HLS":[51,71],"limited":[54],"model":[58,68,99],"parallelization":[59,90],"features.":[60],"In":[61],"this":[62,97],"paper,":[63],"a":[64,81],"generic":[65],"FFT":[66],"usable":[69],"within":[70],"is":[73],"presented.":[74],"Its":[75],"configurable":[76],"parameters":[77],"enable":[78],"to":[79,105],"cover":[80],"broader":[82],"architectural":[83],"space":[84],"taking":[86],"advantage":[87],"more":[89],"strategies":[91],"contrary":[92],"related":[94],"works.":[95],"Thus,":[96],"designed":[98],"can":[100],"produce":[101],"low-complexity":[102],"up":[104],"high":[106],"throughput":[107],"ones":[108],"highlighted":[110],"experimental":[112],"results.":[113]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":2},{"year":2023,"cited_by_count":3}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
