{"id":"https://openalex.org/W4311224548","doi":"https://doi.org/10.1109/icecs202256217.2022.9970882","title":"Novel Design partitioning technique for ASIC prototyping on multi-FPGA platforms using Graph Deep Learning","display_name":"Novel Design partitioning technique for ASIC prototyping on multi-FPGA platforms using Graph Deep Learning","publication_year":2022,"publication_date":"2022-10-24","ids":{"openalex":"https://openalex.org/W4311224548","doi":"https://doi.org/10.1109/icecs202256217.2022.9970882"},"language":"en","primary_location":{"id":"doi:10.1109/icecs202256217.2022.9970882","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecs202256217.2022.9970882","pdf_url":null,"source":{"id":"https://openalex.org/S4363607963","display_name":"2022 29th IEEE International Conference on Electronics, Circuits and Systems (ICECS)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2022 29th IEEE International Conference on Electronics, Circuits and Systems (ICECS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5019871112","display_name":"Divyasree Tummalapalli","orcid":null},"institutions":[{"id":"https://openalex.org/I4210146682","display_name":"Intel (India)","ror":"https://ror.org/04f2n1245","country_code":"IN","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210146682"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"Divyasree Tummalapalli","raw_affiliation_strings":["Intel Corporation,Bengaluru,India","Intel Corporation, Bengaluru, India"],"affiliations":[{"raw_affiliation_string":"Intel Corporation,Bengaluru,India","institution_ids":["https://openalex.org/I4210146682"]},{"raw_affiliation_string":"Intel Corporation, Bengaluru, India","institution_ids":["https://openalex.org/I4210146682"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5045860905","display_name":"Kunapareddy Chiranjeevi","orcid":null},"institutions":[{"id":"https://openalex.org/I4210146682","display_name":"Intel (India)","ror":"https://ror.org/04f2n1245","country_code":"IN","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210146682"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Chiranjeevi Kunapareddy","raw_affiliation_strings":["Intel Corporation,Bengaluru,India","Intel Corporation, Bengaluru, India"],"affiliations":[{"raw_affiliation_string":"Intel Corporation,Bengaluru,India","institution_ids":["https://openalex.org/I4210146682"]},{"raw_affiliation_string":"Intel Corporation, Bengaluru, India","institution_ids":["https://openalex.org/I4210146682"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5071690896","display_name":"Vikas Akalwadi","orcid":null},"institutions":[{"id":"https://openalex.org/I4210146682","display_name":"Intel (India)","ror":"https://ror.org/04f2n1245","country_code":"IN","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210146682"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Vikas Akalwadi","raw_affiliation_strings":["Intel Corporation,Bengaluru,India","Intel Corporation, Bengaluru, India"],"affiliations":[{"raw_affiliation_string":"Intel Corporation,Bengaluru,India","institution_ids":["https://openalex.org/I4210146682"]},{"raw_affiliation_string":"Intel Corporation, Bengaluru, India","institution_ids":["https://openalex.org/I4210146682"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5031569021","display_name":"Rahul Govindan","orcid":"https://orcid.org/0000-0002-9581-0705"},"institutions":[{"id":"https://openalex.org/I4210146682","display_name":"Intel (India)","ror":"https://ror.org/04f2n1245","country_code":"IN","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210146682"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Rahul Govindan","raw_affiliation_strings":["Intel Corporation,Bengaluru,India","Intel Corporation, Bengaluru, India"],"affiliations":[{"raw_affiliation_string":"Intel Corporation,Bengaluru,India","institution_ids":["https://openalex.org/I4210146682"]},{"raw_affiliation_string":"Intel Corporation, Bengaluru, India","institution_ids":["https://openalex.org/I4210146682"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5082698488","display_name":"G Balaji","orcid":null},"institutions":[{"id":"https://openalex.org/I4210146682","display_name":"Intel (India)","ror":"https://ror.org/04f2n1245","country_code":"IN","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210146682"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Balaji G","raw_affiliation_strings":["Intel Corporation,Bengaluru,India","Intel Corporation, Bengaluru, India"],"affiliations":[{"raw_affiliation_string":"Intel Corporation,Bengaluru,India","institution_ids":["https://openalex.org/I4210146682"]},{"raw_affiliation_string":"Intel Corporation, Bengaluru, India","institution_ids":["https://openalex.org/I4210146682"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5019871112"],"corresponding_institution_ids":["https://openalex.org/I4210146682"],"apc_list":null,"apc_paid":null,"fwci":0.3219,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.44706075,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":91,"max":95},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9973999857902527,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8582138419151306},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7806471586227417},{"id":"https://openalex.org/keywords/cluster-analysis","display_name":"Cluster analysis","score":0.7106425762176514},{"id":"https://openalex.org/keywords/application-specific-integrated-circuit","display_name":"Application-specific integrated circuit","score":0.6842038631439209},{"id":"https://openalex.org/keywords/fpga-prototype","display_name":"FPGA prototype","score":0.5330649018287659},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5263489484786987},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.5159952640533447},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.5020256042480469},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.46093645691871643},{"id":"https://openalex.org/keywords/multiplexing","display_name":"Multiplexing","score":0.4441821575164795},{"id":"https://openalex.org/keywords/time-to-market","display_name":"Time to market","score":0.43691155314445496},{"id":"https://openalex.org/keywords/schedule","display_name":"Schedule","score":0.4232363998889923},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.3719276189804077},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3495296835899353},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.23846739530563354}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8582138419151306},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7806471586227417},{"id":"https://openalex.org/C73555534","wikidata":"https://www.wikidata.org/wiki/Q622825","display_name":"Cluster analysis","level":2,"score":0.7106425762176514},{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.6842038631439209},{"id":"https://openalex.org/C203864433","wikidata":"https://www.wikidata.org/wiki/Q5426992","display_name":"FPGA prototype","level":3,"score":0.5330649018287659},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5263489484786987},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.5159952640533447},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.5020256042480469},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.46093645691871643},{"id":"https://openalex.org/C19275194","wikidata":"https://www.wikidata.org/wiki/Q222903","display_name":"Multiplexing","level":2,"score":0.4441821575164795},{"id":"https://openalex.org/C2779229675","wikidata":"https://www.wikidata.org/wiki/Q445235","display_name":"Time to market","level":2,"score":0.43691155314445496},{"id":"https://openalex.org/C68387754","wikidata":"https://www.wikidata.org/wiki/Q7271585","display_name":"Schedule","level":2,"score":0.4232363998889923},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3719276189804077},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3495296835899353},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.23846739530563354},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/icecs202256217.2022.9970882","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecs202256217.2022.9970882","pdf_url":null,"source":{"id":"https://openalex.org/S4363607963","display_name":"2022 29th IEEE International Conference on Electronics, Circuits and Systems (ICECS)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2022 29th IEEE International Conference on Electronics, Circuits and Systems (ICECS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.5400000214576721,"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":18,"referenced_works":["https://openalex.org/W1607118338","https://openalex.org/W2011039300","https://openalex.org/W2083637347","https://openalex.org/W2121947440","https://openalex.org/W2135889985","https://openalex.org/W2152986618","https://openalex.org/W2272158670","https://openalex.org/W2805332017","https://openalex.org/W2964015378","https://openalex.org/W3005144047","https://openalex.org/W3113177135","https://openalex.org/W3188522200","https://openalex.org/W4297733535","https://openalex.org/W6680172340","https://openalex.org/W6726873649","https://openalex.org/W6745537798","https://openalex.org/W6751664678","https://openalex.org/W6787995345"],"related_works":["https://openalex.org/W2108707960","https://openalex.org/W2007173547","https://openalex.org/W2997602288","https://openalex.org/W2152649261","https://openalex.org/W200899231","https://openalex.org/W2356927082","https://openalex.org/W2905116260","https://openalex.org/W2382673458","https://openalex.org/W3162338610","https://openalex.org/W2376218453"],"abstract_inverted_index":{"While":[0],"prototyping":[1],"ASIC":[2],"designs":[3,47,165],"on":[4,126,162],"multi-FPGA":[5,128],"platforms,":[6],"challenges":[7],"like":[8],"partitioning,":[9],"multiplexing":[10],"limited":[11],"I/O":[12],"interconnections":[13],"and":[14,22,149,166,181],"mapping":[15,176],"multiple":[16,49],"clock-domains":[17],"manually,":[18],"cause":[19],"significant":[20],"delays":[21],"unpredictability":[23],"in":[24,59,64,74,97,107,139],"schedule.":[25],"This":[26],"process":[27,44,146],"also":[28],"requires":[29,69],"highly":[30],"skilled":[31],"engineers":[32],"who":[33],"have":[34],"deep":[35],"understanding":[36],"of":[37,45,81,94,147,170],"the":[38,71,75,79,91,104,123,127,135,144,168,171,179],"SoC":[39,164],"designs.":[40],"Automating":[41],"this":[42],"partitioning":[43],"large":[46],"onto":[48,178],"FPGAs":[50],"using":[51],"machine-learning":[52],"techniques":[53],"can":[54],"potentially":[55],"reduce":[56],"time-to-market":[57],"(TTM)":[58],"addition":[60],"to":[61,119,122],"potential":[62],"savings":[63],"engineering":[65],"resources.":[66],"The":[67],"problem":[68],"clustering":[70,148],"various":[72],"IPs":[73,96],"design":[76],"such":[77],"that":[78,141],"number":[80],"signals":[82],"between":[83],"these":[84,114,177],"clusters":[85],"is":[86],"a":[87,98],"minimum,":[88],"while":[89],"ensuring":[90],"total":[92],"resources":[93],"all":[95],"cluster":[99],"does":[100],"not":[101],"go":[102],"beyond":[103],"available":[105],"limit":[106],"an":[108,132],"actual":[109],"FPGA.":[110],"Once":[111],"we":[112,116],"get":[113],"clusters,":[115],"then":[117],"need":[118],"map":[120],"them":[121],"exact":[124],"FPGA":[125],"platform.":[129],"We":[130,154],"propose":[131],"algorithm":[133],"modifying":[134],"GAP":[136],"framework":[137],"proposed":[138],"[4]":[140],"will":[142],"automate":[143],"entire":[145],"mapping,":[150],"eliminating":[151],"human":[152],"intervention.":[153],"see":[155],"good":[156],"quality":[157],"partitions":[158,173],"with":[159],"our":[160],"experiments":[161],"3":[163],"confirmed":[167],"feasibility":[169],"generated":[172],"by":[174],"manually":[175],"hardware":[180],"checking":[182],"routing":[183],"feasibility.":[184]},"counts_by_year":[{"year":2025,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}