{"id":"https://openalex.org/W2914578411","doi":"https://doi.org/10.1109/icecs.2018.8617944","title":"Low Power 16 Phase Ring Oscillator and PLL for Use in sub-ns Time Synchronization over Ethernet","display_name":"Low Power 16 Phase Ring Oscillator and PLL for Use in sub-ns Time Synchronization over Ethernet","publication_year":2018,"publication_date":"2018-12-01","ids":{"openalex":"https://openalex.org/W2914578411","doi":"https://doi.org/10.1109/icecs.2018.8617944","mag":"2914578411"},"language":"en","primary_location":{"id":"doi:10.1109/icecs.2018.8617944","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecs.2018.8617944","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 25th IEEE International Conference on Electronics, Circuits and Systems (ICECS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5064611852","display_name":"Simon Buhr","orcid":"https://orcid.org/0000-0002-6980-2648"},"institutions":[{"id":"https://openalex.org/I78650965","display_name":"TU Dresden","ror":"https://ror.org/042aqky30","country_code":"DE","type":"education","lineage":["https://openalex.org/I78650965"]}],"countries":["DE"],"is_corresponding":true,"raw_author_name":"Simon Buhr","raw_affiliation_strings":["Chair for Circuit Design and Network Theory, Technische Universit\u00e4t Dresden, Dresden, Germany"],"affiliations":[{"raw_affiliation_string":"Chair for Circuit Design and Network Theory, Technische Universit\u00e4t Dresden, Dresden, Germany","institution_ids":["https://openalex.org/I78650965"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5026930933","display_name":"Martin Krei\u00dfig","orcid":"https://orcid.org/0000-0002-2773-9193"},"institutions":[{"id":"https://openalex.org/I78650965","display_name":"TU Dresden","ror":"https://ror.org/042aqky30","country_code":"DE","type":"education","lineage":["https://openalex.org/I78650965"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Martin Kreissig","raw_affiliation_strings":["Chair for Circuit Design and Network Theory, Technische Universit\u00e4t Dresden, Dresden, Germany"],"affiliations":[{"raw_affiliation_string":"Chair for Circuit Design and Network Theory, Technische Universit\u00e4t Dresden, Dresden, Germany","institution_ids":["https://openalex.org/I78650965"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5049816054","display_name":"Frank Ellinger","orcid":"https://orcid.org/0000-0001-6714-0479"},"institutions":[{"id":"https://openalex.org/I78650965","display_name":"TU Dresden","ror":"https://ror.org/042aqky30","country_code":"DE","type":"education","lineage":["https://openalex.org/I78650965"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Frank Ellinger","raw_affiliation_strings":["Chair for Circuit Design and Network Theory, Technische Universit\u00e4t Dresden, Dresden, Germany"],"affiliations":[{"raw_affiliation_string":"Chair for Circuit Design and Network Theory, Technische Universit\u00e4t Dresden, Dresden, Germany","institution_ids":["https://openalex.org/I78650965"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5064611852"],"corresponding_institution_ids":["https://openalex.org/I78650965"],"apc_list":null,"apc_paid":null,"fwci":0.9013,"has_fulltext":false,"cited_by_count":8,"citation_normalized_percentile":{"value":0.77065025,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"53","last_page":"56"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9911999702453613,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9908999800682068,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"Phase-locked loop","score":0.8686810731887817},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.8319168090820312},{"id":"https://openalex.org/keywords/ring-oscillator","display_name":"Ring oscillator","score":0.7123295068740845},{"id":"https://openalex.org/keywords/pll-multibit","display_name":"PLL multibit","score":0.6374840140342712},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.591806173324585},{"id":"https://openalex.org/keywords/synchronization","display_name":"Synchronization (alternating current)","score":0.5750653743743896},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5182207226753235},{"id":"https://openalex.org/keywords/ethernet","display_name":"Ethernet","score":0.5024378299713135},{"id":"https://openalex.org/keywords/clock-synchronization","display_name":"Clock synchronization","score":0.493233859539032},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.47881871461868286},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.41094648838043213},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.33818554878234863},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.27579838037490845},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.2013552188873291},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.16744574904441833},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.14126786589622498}],"concepts":[{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.8686810731887817},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.8319168090820312},{"id":"https://openalex.org/C104111718","wikidata":"https://www.wikidata.org/wiki/Q2153973","display_name":"Ring oscillator","level":3,"score":0.7123295068740845},{"id":"https://openalex.org/C77881186","wikidata":"https://www.wikidata.org/wiki/Q7119642","display_name":"PLL multibit","level":4,"score":0.6374840140342712},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.591806173324585},{"id":"https://openalex.org/C2778562939","wikidata":"https://www.wikidata.org/wiki/Q1298791","display_name":"Synchronization (alternating current)","level":3,"score":0.5750653743743896},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5182207226753235},{"id":"https://openalex.org/C172173386","wikidata":"https://www.wikidata.org/wiki/Q79984","display_name":"Ethernet","level":2,"score":0.5024378299713135},{"id":"https://openalex.org/C129891060","wikidata":"https://www.wikidata.org/wiki/Q1513059","display_name":"Clock synchronization","level":4,"score":0.493233859539032},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.47881871461868286},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.41094648838043213},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.33818554878234863},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.27579838037490845},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.2013552188873291},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.16744574904441833},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.14126786589622498},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/icecs.2018.8617944","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecs.2018.8617944","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 25th IEEE International Conference on Electronics, Circuits and Systems (ICECS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.8899999856948853,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":6,"referenced_works":["https://openalex.org/W1495722529","https://openalex.org/W2114953806","https://openalex.org/W2135441328","https://openalex.org/W2315745911","https://openalex.org/W2343944308","https://openalex.org/W2561920676"],"related_works":["https://openalex.org/W1576949837","https://openalex.org/W984417604","https://openalex.org/W2498262093","https://openalex.org/W2188779191","https://openalex.org/W3134930219","https://openalex.org/W2967785526","https://openalex.org/W188830667","https://openalex.org/W1605914315","https://openalex.org/W4360861688","https://openalex.org/W4376457969"],"abstract_inverted_index":{"A":[0],"16":[1],"Phase":[2],"Ring":[3],"Oscillator":[4],"and":[5,58,75,95],"phase":[6],"locked":[7],"loop":[8],"(PLL)":[9],"suitable":[10],"for":[11,49,60],"time":[12],"synchronization":[13],"with":[14],"down":[15],"to":[16],"500":[17],"ps":[18,82],"accuracy":[19],"via":[20],"Fast":[21],"Ethernet":[22],"is":[23,38,47,64],"presented.":[24],"To":[25],"reduce":[26],"power":[27,41],"consumption":[28,42],"a":[29,67,77],"new":[30],"buffer":[31,46],"stage":[32],"known":[33],"from":[34,73],"CMOS":[35],"level":[36],"shifters":[37],"proposed.":[39],"The":[40,62],"of":[43,80],"the":[44],"output":[45,96],"important":[48],"such":[50],"applications":[51],"where":[52],"all":[53,92],"clock":[54],"phases":[55],"are":[56],"outputted":[57],"used":[59],"synchronization.":[61],"PLL":[63],"fabricated":[65],"in":[66],"low":[68],"cost":[69],"180":[70],"nm":[71],"technology":[72],"GlobalFoundries":[74],"achieves":[76],"RMS":[78],"jitter":[79],"3.2":[81],"at":[83],"125":[84],"MHz":[85],"while":[86],"consuming":[87],"only":[88],"6.1":[89],"mW":[90],"including":[91],"bias":[93],"circuitry":[94],"drivers.":[97]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2020,"cited_by_count":3},{"year":2019,"cited_by_count":4}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}