{"id":"https://openalex.org/W2912619596","doi":"https://doi.org/10.1109/icecs.2018.8617927","title":"Direct Digital Frequency Synthesis design methodology for optimized spurs / jitter performances","display_name":"Direct Digital Frequency Synthesis design methodology for optimized spurs / jitter performances","publication_year":2018,"publication_date":"2018-12-01","ids":{"openalex":"https://openalex.org/W2912619596","doi":"https://doi.org/10.1109/icecs.2018.8617927","mag":"2912619596"},"language":"en","primary_location":{"id":"doi:10.1109/icecs.2018.8617927","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecs.2018.8617927","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 25th IEEE International Conference on Electronics, Circuits and Systems (ICECS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5056550714","display_name":"Gregory Darcheville","orcid":null},"institutions":[{"id":"https://openalex.org/I15057530","display_name":"Universit\u00e9 de Bordeaux","ror":"https://ror.org/057qpr032","country_code":"FR","type":"education","lineage":["https://openalex.org/I15057530"]},{"id":"https://openalex.org/I4210157089","display_name":"Laboratoire de l'Int\u00e9gration du Mat\u00e9riau au Syst\u00e8me","ror":"https://ror.org/04nabhy78","country_code":"FR","type":"facility","lineage":["https://openalex.org/I1294671590","https://openalex.org/I1294671590","https://openalex.org/I15057530","https://openalex.org/I4210091158","https://openalex.org/I4210095849","https://openalex.org/I4210157089","https://openalex.org/I4210160189"]},{"id":"https://openalex.org/I4210160189","display_name":"Institut Polytechnique de Bordeaux","ror":"https://ror.org/054qv7y42","country_code":"FR","type":"education","lineage":["https://openalex.org/I4210160189"]}],"countries":["FR"],"is_corresponding":true,"raw_author_name":"Gregory Darcheville","raw_affiliation_strings":["University of Bordeaux, IMS Laboratory, Talence, France"],"affiliations":[{"raw_affiliation_string":"University of Bordeaux, IMS Laboratory, Talence, France","institution_ids":["https://openalex.org/I4210157089","https://openalex.org/I4210160189","https://openalex.org/I15057530"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5075871119","display_name":"Cyril Voillequin","orcid":null},"institutions":[{"id":"https://openalex.org/I4210140930","display_name":"Thales (France)","ror":"https://ror.org/04emwm605","country_code":"FR","type":"company","lineage":["https://openalex.org/I4210140930"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Cyril Voillequin","raw_affiliation_strings":["Thales Communication & Security, Gennevilliers, France"],"affiliations":[{"raw_affiliation_string":"Thales Communication & Security, Gennevilliers, France","institution_ids":["https://openalex.org/I4210140930"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5109586805","display_name":"Jean-Baptiste B\u00e9gueret","orcid":null},"institutions":[{"id":"https://openalex.org/I15057530","display_name":"Universit\u00e9 de Bordeaux","ror":"https://ror.org/057qpr032","country_code":"FR","type":"education","lineage":["https://openalex.org/I15057530"]},{"id":"https://openalex.org/I4210157089","display_name":"Laboratoire de l'Int\u00e9gration du Mat\u00e9riau au Syst\u00e8me","ror":"https://ror.org/04nabhy78","country_code":"FR","type":"facility","lineage":["https://openalex.org/I1294671590","https://openalex.org/I1294671590","https://openalex.org/I15057530","https://openalex.org/I4210091158","https://openalex.org/I4210095849","https://openalex.org/I4210157089","https://openalex.org/I4210160189"]},{"id":"https://openalex.org/I4210160189","display_name":"Institut Polytechnique de Bordeaux","ror":"https://ror.org/054qv7y42","country_code":"FR","type":"education","lineage":["https://openalex.org/I4210160189"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Jean-Baptiste Begueret","raw_affiliation_strings":["University of Bordeaux, IMS Laboratory, Talence, France"],"affiliations":[{"raw_affiliation_string":"University of Bordeaux, IMS Laboratory, Talence, France","institution_ids":["https://openalex.org/I4210157089","https://openalex.org/I4210160189","https://openalex.org/I15057530"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5056550714"],"corresponding_institution_ids":["https://openalex.org/I15057530","https://openalex.org/I4210157089","https://openalex.org/I4210160189"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.16469092,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"39","issue":null,"first_page":"733","last_page":"736"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.996999979019165,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9937999844551086,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.8007364273071289},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6626103520393372},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.6076443195343018},{"id":"https://openalex.org/keywords/bandwidth","display_name":"Bandwidth (computing)","score":0.5297703742980957},{"id":"https://openalex.org/keywords/lookup-table","display_name":"Lookup table","score":0.5293962359428406},{"id":"https://openalex.org/keywords/direct-digital-synthesizer","display_name":"Direct digital synthesizer","score":0.521238386631012},{"id":"https://openalex.org/keywords/frequency-offset","display_name":"Frequency offset","score":0.5071330070495605},{"id":"https://openalex.org/keywords/accumulator","display_name":"Accumulator (cryptography)","score":0.5057003498077393},{"id":"https://openalex.org/keywords/phase-noise","display_name":"Phase noise","score":0.46194157004356384},{"id":"https://openalex.org/keywords/frequency-synthesizer","display_name":"Frequency synthesizer","score":0.38595762848854065},{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"Phase-locked loop","score":0.3586105704307556},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2239067554473877},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.21438398957252502},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.1649070680141449}],"concepts":[{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.8007364273071289},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6626103520393372},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.6076443195343018},{"id":"https://openalex.org/C2776257435","wikidata":"https://www.wikidata.org/wiki/Q1576430","display_name":"Bandwidth (computing)","level":2,"score":0.5297703742980957},{"id":"https://openalex.org/C134835016","wikidata":"https://www.wikidata.org/wiki/Q690265","display_name":"Lookup table","level":2,"score":0.5293962359428406},{"id":"https://openalex.org/C166089067","wikidata":"https://www.wikidata.org/wiki/Q1227465","display_name":"Direct digital synthesizer","level":5,"score":0.521238386631012},{"id":"https://openalex.org/C49319798","wikidata":"https://www.wikidata.org/wiki/Q5502874","display_name":"Frequency offset","level":4,"score":0.5071330070495605},{"id":"https://openalex.org/C2078106","wikidata":"https://www.wikidata.org/wiki/Q14906620","display_name":"Accumulator (cryptography)","level":2,"score":0.5057003498077393},{"id":"https://openalex.org/C89631360","wikidata":"https://www.wikidata.org/wiki/Q1428766","display_name":"Phase noise","level":2,"score":0.46194157004356384},{"id":"https://openalex.org/C182099602","wikidata":"https://www.wikidata.org/wiki/Q2660678","display_name":"Frequency synthesizer","level":4,"score":0.38595762848854065},{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.3586105704307556},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2239067554473877},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.21438398957252502},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.1649070680141449},{"id":"https://openalex.org/C127162648","wikidata":"https://www.wikidata.org/wiki/Q16858953","display_name":"Channel (broadcasting)","level":2,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C40409654","wikidata":"https://www.wikidata.org/wiki/Q375889","display_name":"Orthogonal frequency-division multiplexing","level":3,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/icecs.2018.8617927","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecs.2018.8617927","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 25th IEEE International Conference on Electronics, Circuits and Systems (ICECS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.5299999713897705,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W342201912","https://openalex.org/W1993610758","https://openalex.org/W1994393408","https://openalex.org/W2008250178","https://openalex.org/W2022123604","https://openalex.org/W2028898228","https://openalex.org/W2098744682","https://openalex.org/W2112276884","https://openalex.org/W2130825290","https://openalex.org/W2539228970","https://openalex.org/W2542955558","https://openalex.org/W6611532385","https://openalex.org/W6652195019"],"related_works":["https://openalex.org/W2166555237","https://openalex.org/W2161572852","https://openalex.org/W2622028395","https://openalex.org/W4386197759","https://openalex.org/W2389258116","https://openalex.org/W2393010087","https://openalex.org/W2015962950","https://openalex.org/W3035420365","https://openalex.org/W4200374561","https://openalex.org/W2798586687"],"abstract_inverted_index":{"The":[0,26,53,69,86,201],"paper":[1],"presents":[2],"a":[3,22,58,73,76,79,82,157,163,170],"simple":[4],"methodology":[5],"to":[6,17,43,46,89,135,209],"choose":[7],"the":[8,19,35,39,63,67,91,95,100,103,108,111,116,119,125,137,152,176,184,207,215,219],"main":[9,92],"parameters":[10,29,93],"of":[11,21,28,34,66,72,94,105,122,142,160,167,172,206,218],"Direct":[12],"Digital":[13,45],"Frequency":[14],"Synthesis":[15],"(DDFS)":[16],"fulfil":[18],"requirements":[20],"given":[23],"communication":[24],"protocol.":[25],"set":[27],"are":[30],"chosen":[31],"in":[32,107,133,140,175],"function":[33],"jitter":[36,145,171],"and":[37,41,81,110,124,127,146,183],"thus":[38],"BER":[40],"leads":[42],"some":[44],"Analog":[47],"Converter":[48],"(DAC)":[49],"phase":[50,74],"noise":[51],"limits.":[52],"method":[54],"described":[55],"relies":[56],"on":[57],"Matlab":[59],"algorithm":[60,87],"that":[61],"calculates":[62],"output":[64,138,199],"tones":[65],"DDFS.":[68],"latter":[70],"consists":[71],"accumulator,":[75],"lookup":[77,112],"table,":[78],"DAC":[80,120],"low":[83],"pass":[84],"filter.":[85],"permits":[88],"define":[90],"DDFS":[96],"blocks":[97],"such":[98],"as":[99],"clock":[101],"frequency,":[102],"number":[104,121],"bits":[106,123],"accumulator":[109],"table":[113],"memory.":[114],"On":[115],"same":[117],"way":[118],"attenuation":[126],"filter":[128],"bandwidth":[129,182],"can":[130],"be":[131,188,210],"estimated":[132],"order":[134],"evaluate":[136],"performances":[139],"terms":[141],"frequency":[143,153,158,194],"resolution,":[144],"spurs":[147,185],"noise.":[148],"In":[149],"our":[150],"application,":[151],"synthesizer":[154],"must":[155,187],"ensure":[156],"step":[159],"100":[161],"Hz,":[162],"fast":[164],"settling":[165],"time":[166],"200":[168],"ns,":[169],"300":[173],"ps":[174],"10":[177],"kHz":[178],"-":[179],"1":[180],"MHz":[181,193],"amplitude":[186],"-70":[189],"dBc":[190],"at":[191,214],"2":[192],"offset":[195],"from":[196],"1.4":[197],"GHz":[198],"frequency.":[200],"simulations":[202],"give":[203],"an":[204],"insight":[205],"challenges":[208],"taken":[211],"into":[212],"account":[213],"initial":[216],"stage":[217],"integrated":[220],"circuit":[221],"design.":[222]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}