{"id":"https://openalex.org/W2913047999","doi":"https://doi.org/10.1109/icecs.2018.8617893","title":"10T and 8T Full Adders Based on Ambipolar XOR Gates with SB-FinFETs","display_name":"10T and 8T Full Adders Based on Ambipolar XOR Gates with SB-FinFETs","publication_year":2018,"publication_date":"2018-12-01","ids":{"openalex":"https://openalex.org/W2913047999","doi":"https://doi.org/10.1109/icecs.2018.8617893","mag":"2913047999"},"language":"en","primary_location":{"id":"doi:10.1109/icecs.2018.8617893","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecs.2018.8617893","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 25th IEEE International Conference on Electronics, Circuits and Systems (ICECS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5013991946","display_name":"Talha Furkan Canan","orcid":"https://orcid.org/0000-0002-7154-3622"},"institutions":[{"id":"https://openalex.org/I4210106879","display_name":"Ohio University","ror":"https://ror.org/01jr3y717","country_code":"US","type":"education","lineage":["https://openalex.org/I4210106879"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Talha Furkan Canan","raw_affiliation_strings":["School of Elec. Eng. & Comp. Sci., Ohio University, Athens, OH, USA"],"affiliations":[{"raw_affiliation_string":"School of Elec. Eng. & Comp. Sci., Ohio University, Athens, OH, USA","institution_ids":["https://openalex.org/I4210106879"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5035472753","display_name":"Sava\u015f Kaya","orcid":"https://orcid.org/0000-0002-6010-1271"},"institutions":[{"id":"https://openalex.org/I138006243","display_name":"University of Arizona","ror":"https://ror.org/03m2x1q45","country_code":"US","type":"education","lineage":["https://openalex.org/I138006243"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Savas Kaya","raw_affiliation_strings":["Dept. of Elec. & Comp. Eng., University of Arizona, Tucson, AZ, USA"],"affiliations":[{"raw_affiliation_string":"Dept. of Elec. & Comp. Eng., University of Arizona, Tucson, AZ, USA","institution_ids":["https://openalex.org/I138006243"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5014895124","display_name":"Avinash Karanth","orcid":"https://orcid.org/0000-0002-9472-4637"},"institutions":[{"id":"https://openalex.org/I193531525","display_name":"George Washington University","ror":"https://ror.org/00y4zzh67","country_code":"US","type":"education","lineage":["https://openalex.org/I193531525"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Avinash Kodi","raw_affiliation_strings":["Dept. of Elec. & Comp. Eng., George Washington University, Washington, DC, USA"],"affiliations":[{"raw_affiliation_string":"Dept. of Elec. & Comp. Eng., George Washington University, Washington, DC, USA","institution_ids":["https://openalex.org/I193531525"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101805370","display_name":"Hao Xin","orcid":"https://orcid.org/0000-0002-0815-8828"},"institutions":[{"id":"https://openalex.org/I4210106879","display_name":"Ohio University","ror":"https://ror.org/01jr3y717","country_code":"US","type":"education","lineage":["https://openalex.org/I4210106879"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Hao Xin","raw_affiliation_strings":["School of Elec. Eng. & Comp. Sci., Ohio University, Athens, OH, USA"],"affiliations":[{"raw_affiliation_string":"School of Elec. Eng. & Comp. Sci., Ohio University, Athens, OH, USA","institution_ids":["https://openalex.org/I4210106879"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5034189643","display_name":"Ahmed Louri","orcid":"https://orcid.org/0000-0003-4262-6688"},"institutions":[{"id":"https://openalex.org/I4210106879","display_name":"Ohio University","ror":"https://ror.org/01jr3y717","country_code":"US","type":"education","lineage":["https://openalex.org/I4210106879"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Ahmed Louri","raw_affiliation_strings":["School of Elec. Eng. & Comp. Sci., Ohio University, Athens, OH, USA"],"affiliations":[{"raw_affiliation_string":"School of Elec. Eng. & Comp. Sci., Ohio University, Athens, OH, USA","institution_ids":["https://openalex.org/I4210106879"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5013991946"],"corresponding_institution_ids":["https://openalex.org/I4210106879"],"apc_list":null,"apc_paid":null,"fwci":0.1288,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.51991494,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":95},"biblio":{"volume":null,"issue":null,"first_page":"577","last_page":"580"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.8338640928268433},{"id":"https://openalex.org/keywords/xor-gate","display_name":"XOR gate","score":0.7820021510124207},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.7142564058303833},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.6422536969184875},{"id":"https://openalex.org/keywords/pass-transistor-logic","display_name":"Pass transistor logic","score":0.5886390805244446},{"id":"https://openalex.org/keywords/and-or-invert","display_name":"AND-OR-Invert","score":0.5643742084503174},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5587027668952942},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5555531978607178},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.5157990455627441},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.49621516466140747},{"id":"https://openalex.org/keywords/nand-gate","display_name":"NAND gate","score":0.4790031611919403},{"id":"https://openalex.org/keywords/propagation-delay","display_name":"Propagation delay","score":0.4557565748691559},{"id":"https://openalex.org/keywords/ambipolar-diffusion","display_name":"Ambipolar diffusion","score":0.42777276039123535},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.42516815662384033},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.38769620656967163},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.3404419422149658},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.3174252510070801},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2200152575969696},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.1876024305820465},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.10404881834983826}],"concepts":[{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.8338640928268433},{"id":"https://openalex.org/C28495749","wikidata":"https://www.wikidata.org/wiki/Q155516","display_name":"XOR gate","level":3,"score":0.7820021510124207},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.7142564058303833},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6422536969184875},{"id":"https://openalex.org/C198521697","wikidata":"https://www.wikidata.org/wiki/Q7142438","display_name":"Pass transistor logic","level":4,"score":0.5886390805244446},{"id":"https://openalex.org/C130126468","wikidata":"https://www.wikidata.org/wiki/Q4652943","display_name":"AND-OR-Invert","level":5,"score":0.5643742084503174},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5587027668952942},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5555531978607178},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.5157990455627441},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.49621516466140747},{"id":"https://openalex.org/C124296912","wikidata":"https://www.wikidata.org/wiki/Q575178","display_name":"NAND gate","level":3,"score":0.4790031611919403},{"id":"https://openalex.org/C90806461","wikidata":"https://www.wikidata.org/wiki/Q1144416","display_name":"Propagation delay","level":2,"score":0.4557565748691559},{"id":"https://openalex.org/C25621703","wikidata":"https://www.wikidata.org/wiki/Q2658857","display_name":"Ambipolar diffusion","level":3,"score":0.42777276039123535},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.42516815662384033},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.38769620656967163},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.3404419422149658},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.3174252510070801},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2200152575969696},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.1876024305820465},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.10404881834983826},{"id":"https://openalex.org/C82706917","wikidata":"https://www.wikidata.org/wiki/Q10251","display_name":"Plasma","level":2,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/icecs.2018.8617893","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecs.2018.8617893","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 25th IEEE International Conference on Electronics, Circuits and Systems (ICECS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320306076","display_name":"National Science Foundation","ror":"https://ror.org/021nxhr62"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W2084006301","https://openalex.org/W2117379410","https://openalex.org/W2127587406","https://openalex.org/W2165122009","https://openalex.org/W2339660142","https://openalex.org/W2396174493","https://openalex.org/W2553781108","https://openalex.org/W2586279097","https://openalex.org/W2595507424","https://openalex.org/W2756683678","https://openalex.org/W2778944598","https://openalex.org/W2782536487","https://openalex.org/W4243164749"],"related_works":["https://openalex.org/W2789662562","https://openalex.org/W4214735176","https://openalex.org/W2601542976","https://openalex.org/W2184476805","https://openalex.org/W3186520623","https://openalex.org/W1901807635","https://openalex.org/W2963778543","https://openalex.org/W2168217865","https://openalex.org/W1979361505","https://openalex.org/W2786283752"],"abstract_inverted_index":{"We":[0],"introduce":[1],"novel":[2,52,91,107,139],"ten":[3],"(10T)":[4],"and":[5,36,54,93,118,182],"eight":[6],"(8T)":[7],"transistor":[8],"full-adder":[9,120],"logic":[10,87,188],"gates":[11,57,96,108],"based":[12],"on":[13],"recently":[14],"proposed":[15],"gate":[16,74],"workfunction":[17],"engineering":[18],"(WFE)":[19],"approach.":[20],"When":[21],"applied":[22],"to":[23,32,103,112,127,150],"sub-10":[24],"nm":[25],"Schottky-barrier":[26],"(SB)":[27],"independent-gate":[28],"FinFETs,":[29],"WFE":[30,175],"leads":[31],"hitherto":[33],"unexplored":[34],"4T":[35,53,92],"3T":[37,55,94],"XOR":[38,56,95],"implementations":[39],"that":[40,65,191],"operate":[41],"with":[42],"either":[43],"only":[44],"one":[45],"or":[46],"no":[47],"inverted":[48,62],"input,":[49],"respectively.":[50],"The":[51],"eliminate":[58],"the":[59,72,77,86,90,138,151,162,170,173],"need":[60],"for":[61,186],"inputs":[63],"provided":[64],"ambipolar":[66],"I-V":[67],"characteristics":[68],"is":[69],"shifted":[70],"by":[71],"associated":[73],"work-function":[75],"in":[76,114,130,145,154,166,178],"right":[78],"direction,":[79],"where":[80],"another":[81],"conduction":[82],"channel":[83],"exists.":[84],"Following":[85],"verification":[88],"of":[89,137,164],"via":[97],"TCAD":[98],"simulations,":[99],"we":[100],"then":[101],"continue":[102],"show":[104,141],"how":[105],"these":[106],"can":[109,192],"be":[110,193],"put":[111],"use":[113],"building":[115,189],"ultra-compact":[116],"10T":[117],"8T":[119],"circuits,":[121],"which":[122],"would":[123],"normally":[124],"require":[125],"up":[126],"20":[128],"FinFETs":[129],"conventional":[131],"CMOS":[132],"architecture.":[133],"Simulated":[134],"power-delay":[135],"products":[136],"full-adders":[140,171],"significant":[142],"(~5\u00d7)":[143],"improvement":[144],"dynamic":[146],"performance":[147,183],"attributed":[148],"largely":[149],"50%":[152],"reduction":[153],"total":[155],"area":[156,181],"as":[157,159],"well":[158],"parasitics,":[160],"at":[161],"expense":[163],"loss":[165],"noise":[167],"margins.":[168],"Besides":[169],"explored,":[172],"presented":[174],"approach":[176],"could":[177],"general":[179],"provide":[180],"gains":[184],"also":[185],"other":[187],"blocks":[190],"redesigned":[194],"using":[195],"SB-FinFETs.":[196]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2021,"cited_by_count":1}],"updated_date":"2026-01-13T01:12:25.745995","created_date":"2025-10-10T00:00:00"}