{"id":"https://openalex.org/W2913130713","doi":"https://doi.org/10.1109/icecs.2018.8617879","title":"Logic-In-Memory Architecture For Min/Max Search","display_name":"Logic-In-Memory Architecture For Min/Max Search","publication_year":2018,"publication_date":"2018-12-01","ids":{"openalex":"https://openalex.org/W2913130713","doi":"https://doi.org/10.1109/icecs.2018.8617879","mag":"2913130713"},"language":"en","primary_location":{"id":"doi:10.1109/icecs.2018.8617879","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecs.2018.8617879","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 25th IEEE International Conference on Electronics, Circuits and Systems (ICECS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5012025330","display_name":"Marco Vacca","orcid":"https://orcid.org/0000-0003-2920-3357"},"institutions":[{"id":"https://openalex.org/I177477856","display_name":"Polytechnic University of Turin","ror":"https://ror.org/00bgk9508","country_code":"IT","type":"education","lineage":["https://openalex.org/I177477856"]}],"countries":["IT"],"is_corresponding":true,"raw_author_name":"Marco Vacca","raw_affiliation_strings":["Department of Electronics and Telecommunications, Politecnico di Torino, Italy"],"affiliations":[{"raw_affiliation_string":"Department of Electronics and Telecommunications, Politecnico di Torino, Italy","institution_ids":["https://openalex.org/I177477856"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5021204371","display_name":"Yaswanth Tavva","orcid":"https://orcid.org/0000-0002-5251-288X"},"institutions":[{"id":"https://openalex.org/I172675005","display_name":"Nanyang Technological University","ror":"https://ror.org/02e7b5302","country_code":"SG","type":"education","lineage":["https://openalex.org/I172675005"]}],"countries":["SG"],"is_corresponding":false,"raw_author_name":"Yaswanth Tavva","raw_affiliation_strings":["School of Computer Science and Engineering, Nanyang Technological University, Singapore"],"affiliations":[{"raw_affiliation_string":"School of Computer Science and Engineering, Nanyang Technological University, Singapore","institution_ids":["https://openalex.org/I172675005"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5089860351","display_name":"Anupam Chattopadhyay","orcid":"https://orcid.org/0000-0002-8818-6983"},"institutions":[{"id":"https://openalex.org/I172675005","display_name":"Nanyang Technological University","ror":"https://ror.org/02e7b5302","country_code":"SG","type":"education","lineage":["https://openalex.org/I172675005"]}],"countries":["SG"],"is_corresponding":false,"raw_author_name":"Anupam Chattopadhyay","raw_affiliation_strings":["School of Computer Science and Engineering, Nanyang Technological University, Singapore"],"affiliations":[{"raw_affiliation_string":"School of Computer Science and Engineering, Nanyang Technological University, Singapore","institution_ids":["https://openalex.org/I172675005"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5034581393","display_name":"Andrea Calimera","orcid":"https://orcid.org/0000-0001-5881-3811"},"institutions":[{"id":"https://openalex.org/I177477856","display_name":"Polytechnic University of Turin","ror":"https://ror.org/00bgk9508","country_code":"IT","type":"education","lineage":["https://openalex.org/I177477856"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Andrea Calimera","raw_affiliation_strings":["Department of Control and Computer Engineering, Politecnico di Torino, Italy"],"affiliations":[{"raw_affiliation_string":"Department of Control and Computer Engineering, Politecnico di Torino, Italy","institution_ids":["https://openalex.org/I177477856"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5012025330"],"corresponding_institution_ids":["https://openalex.org/I177477856"],"apc_list":null,"apc_paid":null,"fwci":0.5536,"has_fulltext":false,"cited_by_count":7,"citation_normalized_percentile":{"value":0.72151681,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":94,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"853","last_page":"856"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11321","display_name":"Error Correcting Code Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11321","display_name":"Error Correcting Code Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11269","display_name":"Algorithms and Data Compression","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.995199978351593,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6297554969787598},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.5784060955047607},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.42650306224823},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.39323484897613525},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.3224843144416809},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.20841577649116516}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6297554969787598},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.5784060955047607},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.42650306224823},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.39323484897613525},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.3224843144416809},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.20841577649116516},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/icecs.2018.8617879","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecs.2018.8617879","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 25th IEEE International Conference on Electronics, Circuits and Systems (ICECS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.9100000262260437}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W1979629957","https://openalex.org/W2013435193","https://openalex.org/W2052346850","https://openalex.org/W2085671259","https://openalex.org/W2123889627","https://openalex.org/W2156429183","https://openalex.org/W2612905056","https://openalex.org/W2756701274","https://openalex.org/W2766489088","https://openalex.org/W2768113514"],"related_works":["https://openalex.org/W2748952813","https://openalex.org/W2390279801","https://openalex.org/W2358668433","https://openalex.org/W2376932109","https://openalex.org/W2001405890","https://openalex.org/W2382290278","https://openalex.org/W2478288626","https://openalex.org/W4391913857","https://openalex.org/W2350741829","https://openalex.org/W2038503502"],"abstract_inverted_index":{"Algorithms":[0],"for":[1,68,139],"data-analytics":[2],"executed":[3],"on":[4,126],"classical":[5],"Von":[6],"Neumann":[7],"architectures":[8,67],"proved":[9],"highly":[10],"energy":[11,137],"inefficient.":[12],"In-Memory":[13],"Computing":[14],"have":[15],"been":[16,110],"indicated":[17],"as":[18,81,86,142,144],"a":[19,33,46,82,127,147],"practical":[20],"solution":[21],"to":[22,26,45,112],"improve":[23],"speed":[24],"and":[25,74,85,146],"reduce":[27],"power":[28,76],"consumption.":[29,77],"This":[30],"work":[31],"introduces":[32],"new":[34,60],"memory":[35,120],"architecture":[36],"that":[37],"extends":[38],"the":[39,64,105,114,118],"use":[40],"of":[41,53,66,104,117,151],"bit-wise":[42],"logic":[43],"operations":[44],"more":[47],"complex":[48],"iterative":[49],"algorithm,":[50],"i.e.,":[51],"search":[52,107],"minimum/maximum":[54,69,106],"values":[55],"across":[56],"bulk":[57],"data.":[58],"Such":[59],"design":[61],"preserves":[62],"all":[63],"characteristics":[65],"detection,":[70],"achieving":[71],"high":[72],"performance":[73],"low":[75,143],"It":[78,90],"serves":[79],"both":[80],"local":[83],"memory,":[84],"an":[87,136],"acceleration":[88],"engine.":[89],"can":[91],"be":[92],"implemented":[93],"with":[94,98,135],"MOS":[95],"transistors":[96],"or":[97],"emerging":[99],"devices.":[100],"A":[101,122],"novel":[102],"implementation":[103],"algorithm":[108],"has":[109],"tailored":[111],"fit":[113],"internal":[115],"organization":[116],"proposed":[119],"architecture.":[121],"parametric":[123],"analysis":[124],"conducted":[125],"28nm":[128],"FDSOI":[129],"CMOS":[130],"technology":[131],"highlights":[132],"remarkable":[133],"results,":[134],"consumption":[138],"single":[140],"bit":[141],"0.09fJ":[145],"maximum":[148],"operating":[149],"frequency":[150],"2GHz.":[152]},"counts_by_year":[{"year":2024,"cited_by_count":2},{"year":2022,"cited_by_count":2},{"year":2021,"cited_by_count":3}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
