{"id":"https://openalex.org/W2585935494","doi":"https://doi.org/10.1109/icecs.2016.7841253","title":"Ultra-low voltage standard cell libraries: Design strategies and a case study","display_name":"Ultra-low voltage standard cell libraries: Design strategies and a case study","publication_year":2016,"publication_date":"2016-12-01","ids":{"openalex":"https://openalex.org/W2585935494","doi":"https://doi.org/10.1109/icecs.2016.7841253","mag":"2585935494"},"language":"en","primary_location":{"id":"doi:10.1109/icecs.2016.7841253","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecs.2016.7841253","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5038449373","display_name":"Somayeh Timarchi","orcid":null},"institutions":[{"id":"https://openalex.org/I48379061","display_name":"Shahid Beheshti University","ror":"https://ror.org/0091vmj44","country_code":"IR","type":"education","lineage":["https://openalex.org/I48379061"]}],"countries":["IR"],"is_corresponding":true,"raw_author_name":"Somayeh Timarchi","raw_affiliation_strings":["Electrical Engineering Department, Shahid Beheshti University, Tehran, Iran"],"affiliations":[{"raw_affiliation_string":"Electrical Engineering Department, Shahid Beheshti University, Tehran, Iran","institution_ids":["https://openalex.org/I48379061"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5052037141","display_name":"Massimo Alioto","orcid":"https://orcid.org/0000-0002-4127-8258"},"institutions":[{"id":"https://openalex.org/I165932596","display_name":"National University of Singapore","ror":"https://ror.org/01tgyzw49","country_code":"SG","type":"education","lineage":["https://openalex.org/I165932596"]}],"countries":["SG"],"is_corresponding":false,"raw_author_name":"Massimo Alioto","raw_affiliation_strings":["ECE Dept., National University of Singapore, Singapore"],"affiliations":[{"raw_affiliation_string":"ECE Dept., National University of Singapore, Singapore","institution_ids":["https://openalex.org/I165932596"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5038449373"],"corresponding_institution_ids":["https://openalex.org/I48379061"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.1655063,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"520","last_page":"523"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/standard-cell","display_name":"Standard cell","score":0.8860017657279968},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.776069700717926},{"id":"https://openalex.org/keywords/low-voltage","display_name":"Low voltage","score":0.7531756162643433},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.5647186040878296},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5300498008728027},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.5069670677185059},{"id":"https://openalex.org/keywords/threshold-voltage","display_name":"Threshold voltage","score":0.4881463944911957},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4736417829990387},{"id":"https://openalex.org/keywords/integrated-circuit-design","display_name":"Integrated circuit design","score":0.4521607756614685},{"id":"https://openalex.org/keywords/design-methods","display_name":"Design methods","score":0.45083558559417725},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.3356166183948517},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.2579578161239624},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2468073070049286},{"id":"https://openalex.org/keywords/mechanical-engineering","display_name":"Mechanical engineering","score":0.08217129111289978}],"concepts":[{"id":"https://openalex.org/C78401558","wikidata":"https://www.wikidata.org/wiki/Q464496","display_name":"Standard cell","level":3,"score":0.8860017657279968},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.776069700717926},{"id":"https://openalex.org/C128624480","wikidata":"https://www.wikidata.org/wiki/Q1504817","display_name":"Low voltage","level":3,"score":0.7531756162643433},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.5647186040878296},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5300498008728027},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.5069670677185059},{"id":"https://openalex.org/C195370968","wikidata":"https://www.wikidata.org/wiki/Q1754002","display_name":"Threshold voltage","level":4,"score":0.4881463944911957},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4736417829990387},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.4521607756614685},{"id":"https://openalex.org/C138852830","wikidata":"https://www.wikidata.org/wiki/Q2292993","display_name":"Design methods","level":2,"score":0.45083558559417725},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.3356166183948517},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.2579578161239624},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2468073070049286},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.08217129111289978}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/icecs.2016.7841253","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecs.2016.7841253","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W649475307","https://openalex.org/W1972131277","https://openalex.org/W1974982221","https://openalex.org/W2017216250","https://openalex.org/W2097579177","https://openalex.org/W2133256259","https://openalex.org/W3212618473"],"related_works":["https://openalex.org/W2585935494","https://openalex.org/W2045408571","https://openalex.org/W1564892798","https://openalex.org/W2799803723","https://openalex.org/W2808428854","https://openalex.org/W2577477803","https://openalex.org/W2991342931","https://openalex.org/W1965232212","https://openalex.org/W2772390328","https://openalex.org/W2151657833"],"abstract_inverted_index":{"In":[0],"this":[1,42],"paper,":[2],"design":[3,8,82,88],"guidelines":[4],"and":[5,55,60,68],"criteria":[6,32],"to":[7,26,31,51,58,64,87],"ultra-low":[9,23,48,71],"voltage":[10,72],"standard":[11,94,102],"cell":[12,95,103],"libraries":[13,21],"are":[14,34,53,74,84],"introduced":[15],"in":[16,107],"a":[17,98,101],"unitary":[18],"framework.":[19],"Indeed,":[20],"for":[22],"voltages":[24,49],"need":[25],"be":[27],"fully":[28],"redesigned":[29],"according":[30,57],"that":[33],"very":[35],"different":[36],"from":[37],"traditional":[38],"above-threshold":[39],"libraries.":[40],"To":[41],"aim,":[43],"critical":[44],"issues":[45,67],"arising":[46],"at":[47,76],"down":[50],"sub-threshold":[52],"identified":[54],"analyzed":[56],"simple":[59],"general":[61],"principles.":[62],"Guidelines":[63],"address":[65],"these":[66],"enable":[69],"robust":[70],"operation":[73],"derived":[75],"the":[77,89,92],"transistor":[78],"level.":[79],"The":[80],"same":[81],"principles":[83],"also":[85],"employed":[86],"composition":[90],"of":[91],"CMOS":[93,109],"library.":[96],"As":[97],"case":[99],"study,":[100],"library":[104],"is":[105],"designed":[106],"180-nm":[108],"technology.":[110]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2020,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
