{"id":"https://openalex.org/W2583940779","doi":"https://doi.org/10.1109/icecs.2016.7841211","title":"Logic filter cache for wide-VDD-range processors","display_name":"Logic filter cache for wide-VDD-range processors","publication_year":2016,"publication_date":"2016-12-01","ids":{"openalex":"https://openalex.org/W2583940779","doi":"https://doi.org/10.1109/icecs.2016.7841211","mag":"2583940779"},"language":"en","primary_location":{"id":"doi:10.1109/icecs.2016.7841211","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecs.2016.7841211","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"http://publications.lib.chalmers.se/records/fulltext/246156/local_246156.pdf","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5048252132","display_name":"Alen Bardizbanyan","orcid":null},"institutions":[{"id":"https://openalex.org/I66862912","display_name":"Chalmers University of Technology","ror":"https://ror.org/040wg7k59","country_code":"SE","type":"education","lineage":["https://openalex.org/I66862912"]}],"countries":["SE"],"is_corresponding":true,"raw_author_name":"Alen Bardizbanyan","raw_affiliation_strings":["Chalmers University of Technology, Gothenburg, Sweden"],"affiliations":[{"raw_affiliation_string":"Chalmers University of Technology, Gothenburg, Sweden","institution_ids":["https://openalex.org/I66862912"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5019912356","display_name":"Oskar Andersson","orcid":"https://orcid.org/0000-0003-1663-5599"},"institutions":[{"id":"https://openalex.org/I66862912","display_name":"Chalmers University of Technology","ror":"https://ror.org/040wg7k59","country_code":"SE","type":"education","lineage":["https://openalex.org/I66862912"]}],"countries":["SE"],"is_corresponding":false,"raw_author_name":"Oskar Andersson","raw_affiliation_strings":["Chalmers University of Technology, Gothenburg, Sweden"],"affiliations":[{"raw_affiliation_string":"Chalmers University of Technology, Gothenburg, Sweden","institution_ids":["https://openalex.org/I66862912"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5104061156","display_name":"Joachim Rodrigues","orcid":null},"institutions":[{"id":"https://openalex.org/I66862912","display_name":"Chalmers University of Technology","ror":"https://ror.org/040wg7k59","country_code":"SE","type":"education","lineage":["https://openalex.org/I66862912"]}],"countries":["SE"],"is_corresponding":false,"raw_author_name":"Joachim Rodrigues","raw_affiliation_strings":["Chalmers University of Technology, Gothenburg, Sweden"],"affiliations":[{"raw_affiliation_string":"Chalmers University of Technology, Gothenburg, Sweden","institution_ids":["https://openalex.org/I66862912"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5053343948","display_name":"Per Larsson-Edefors","orcid":"https://orcid.org/0000-0001-5779-4313"},"institutions":[{"id":"https://openalex.org/I66862912","display_name":"Chalmers University of Technology","ror":"https://ror.org/040wg7k59","country_code":"SE","type":"education","lineage":["https://openalex.org/I66862912"]}],"countries":["SE"],"is_corresponding":false,"raw_author_name":"Per Larsson-Edefors","raw_affiliation_strings":["Chalmers University of Technology, Gothenburg, Sweden"],"affiliations":[{"raw_affiliation_string":"Chalmers University of Technology, Gothenburg, Sweden","institution_ids":["https://openalex.org/I66862912"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5048252132"],"corresponding_institution_ids":["https://openalex.org/I66862912"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":true,"cited_by_count":0,"citation_normalized_percentile":{"value":0.1815758,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"51","issue":null,"first_page":"376","last_page":"379"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.871503472328186},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7335049510002136},{"id":"https://openalex.org/keywords/cache-algorithms","display_name":"Cache algorithms","score":0.6880921125411987},{"id":"https://openalex.org/keywords/page-cache","display_name":"Page cache","score":0.683361291885376},{"id":"https://openalex.org/keywords/smart-cache","display_name":"Smart Cache","score":0.6507707238197327},{"id":"https://openalex.org/keywords/cache-pollution","display_name":"Cache pollution","score":0.633411169052124},{"id":"https://openalex.org/keywords/cache-coloring","display_name":"Cache coloring","score":0.5832219123840332},{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.5443486571311951},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5339100956916809},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.5259870886802673},{"id":"https://openalex.org/keywords/cache-invalidation","display_name":"Cache invalidation","score":0.48098552227020264},{"id":"https://openalex.org/keywords/cache-oblivious-algorithm","display_name":"Cache-oblivious algorithm","score":0.4150428771972656},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3759670853614807},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.2477920651435852}],"concepts":[{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.871503472328186},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7335049510002136},{"id":"https://openalex.org/C38556500","wikidata":"https://www.wikidata.org/wiki/Q13404475","display_name":"Cache algorithms","level":4,"score":0.6880921125411987},{"id":"https://openalex.org/C36340418","wikidata":"https://www.wikidata.org/wiki/Q7124288","display_name":"Page cache","level":5,"score":0.683361291885376},{"id":"https://openalex.org/C167713795","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"Smart Cache","level":5,"score":0.6507707238197327},{"id":"https://openalex.org/C113166858","wikidata":"https://www.wikidata.org/wiki/Q5015981","display_name":"Cache pollution","level":5,"score":0.633411169052124},{"id":"https://openalex.org/C201148951","wikidata":"https://www.wikidata.org/wiki/Q5015976","display_name":"Cache coloring","level":4,"score":0.5832219123840332},{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.5443486571311951},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5339100956916809},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.5259870886802673},{"id":"https://openalex.org/C25536678","wikidata":"https://www.wikidata.org/wiki/Q5015977","display_name":"Cache invalidation","level":5,"score":0.48098552227020264},{"id":"https://openalex.org/C59687516","wikidata":"https://www.wikidata.org/wiki/Q5015938","display_name":"Cache-oblivious algorithm","level":5,"score":0.4150428771972656},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3759670853614807},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.2477920651435852}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1109/icecs.2016.7841211","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecs.2016.7841211","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS)","raw_type":"proceedings-article"},{"id":"pmh:oai:research.chalmers.se:246156","is_oa":true,"landing_page_url":"https://research.chalmers.se/en/publication/246156","pdf_url":"http://publications.lib.chalmers.se/records/fulltext/246156/local_246156.pdf","source":{"id":"https://openalex.org/S4306402469","display_name":"Chalmers Research (Chalmers University of Technology)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I66862912","host_organization_name":"Chalmers University of Technology","host_organization_lineage":["https://openalex.org/I66862912"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":""},{"id":"pmh:oai:lup.lub.lu.se:f309dd40-3237-40d8-9a58-0734864ff23e","is_oa":false,"landing_page_url":"https://lup.lub.lu.se/record/f309dd40-3237-40d8-9a58-0734864ff23e","pdf_url":null,"source":{"id":"https://openalex.org/S4306400536","display_name":"Lund University Publications (Lund University)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I187531555","host_organization_name":"Lund University","host_organization_lineage":["https://openalex.org/I187531555"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"text"}],"best_oa_location":{"id":"pmh:oai:research.chalmers.se:246156","is_oa":true,"landing_page_url":"https://research.chalmers.se/en/publication/246156","pdf_url":"http://publications.lib.chalmers.se/records/fulltext/246156/local_246156.pdf","source":{"id":"https://openalex.org/S4306402469","display_name":"Chalmers Research (Chalmers University of Technology)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I66862912","host_organization_name":"Chalmers University of Technology","host_organization_lineage":["https://openalex.org/I66862912"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":""},"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.8999999761581421,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"pdf":true,"grobid_xml":true},"content_urls":{"pdf":"https://content.openalex.org/works/W2583940779.pdf","grobid_xml":"https://content.openalex.org/works/W2583940779.grobid-xml"},"referenced_works_count":16,"referenced_works":["https://openalex.org/W1686420892","https://openalex.org/W1998525920","https://openalex.org/W2020875745","https://openalex.org/W2029320584","https://openalex.org/W2072880927","https://openalex.org/W2094960953","https://openalex.org/W2104225326","https://openalex.org/W2128748528","https://openalex.org/W2145191373","https://openalex.org/W2147435261","https://openalex.org/W2169353948","https://openalex.org/W2281229150","https://openalex.org/W3148936090","https://openalex.org/W4235455150","https://openalex.org/W4248463787","https://openalex.org/W6637151178"],"related_works":["https://openalex.org/W2098406302","https://openalex.org/W2535115842","https://openalex.org/W2734782074","https://openalex.org/W2546991807","https://openalex.org/W2020176098","https://openalex.org/W2006655698","https://openalex.org/W2436169747","https://openalex.org/W2121191383","https://openalex.org/W2076114130","https://openalex.org/W2116323004"],"abstract_inverted_index":{"Wide-VDD-range":[0],"processors":[1],"offer":[2],"high":[3],"energy":[4,152],"efficiency":[5],"for":[6],"varying":[7],"embedded":[8],"workloads.":[9],"But":[10],"reducing":[11],"the":[12,15,20,23,52,58,80,84,91,144,148,171],"VDD":[13,21,54,99,128],"of":[14,22,73,87,108,129,170],"cache":[16,61,78,82,93,109,146,150,173],"as":[17,19,97],"aggressively":[18],"CPU":[24,53,98,125],"logic":[25,48],"is":[26,100,168],"not":[27],"straightforward,":[28],"since":[29],"standard":[30],"6T":[31],"SRAMs":[32],"cease":[33],"to":[34,56,62,102],"operate":[35],"at":[36,66,155,160,163],"lower":[37],"VDDs.":[38],"We":[39,111],"implement":[40],"a":[41,67,116,123],"data":[42],"and":[43,126,131,139,158],"instruction":[44],"filter":[45,81,92,103,141,145],"cache,":[46],"using":[47,115],"cells":[49],"located":[50],"in":[51],"domain,":[55],"permit":[57],"level-1":[59],"(L1)":[60],"be":[63,95],"reliably":[64],"powered":[65],"higher":[68],"SRAM":[69,127],"VDD.":[70],"On":[71],"top":[72],"eliminating":[74],"many":[75],"energy-wasting":[76],"L1":[77,137,172],"accesses,":[79],"reduces":[83,147],"total":[85,149],"number":[86],"executed":[88],"cycles.":[89],"Furthermore,":[90],"can":[94],"reconfigured":[96],"reduced,":[101],"out":[104],"an":[105,164],"increasing":[106],"proportion":[107],"accesses.":[110],"evaluate":[112],"our":[113],"approach":[114],"65-nm":[117],"1.2-V":[118],"low-leakage":[119],"CMOS":[120],"process,":[121],"with":[122],"minimal":[124],"0.4":[130,161],"0.95":[132],"V,":[133],"respectively.":[134],"Assuming":[135],"16kB+16kB":[136],"caches":[138],"256B+256B":[140],"caches,":[142],"introducing":[143],"access":[151],"by":[153],"71%":[154],"1.2":[156],"V":[157,162],"87%":[159],"area":[165],"overhead":[166],"which":[167],"13%":[169],"area.":[174]},"counts_by_year":[],"updated_date":"2026-03-10T16:38:18.471706","created_date":"2025-10-10T00:00:00"}