{"id":"https://openalex.org/W2306841542","doi":"https://doi.org/10.1109/icecs.2015.7440387","title":"Deadlock detection in conditional asynchronous circuits under mismatched branch selection","display_name":"Deadlock detection in conditional asynchronous circuits under mismatched branch selection","publication_year":2015,"publication_date":"2015-12-01","ids":{"openalex":"https://openalex.org/W2306841542","doi":"https://doi.org/10.1109/icecs.2015.7440387","mag":"2306841542"},"language":"en","primary_location":{"id":"doi:10.1109/icecs.2015.7440387","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecs.2015.7440387","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5084741373","display_name":"Eslam Yahya","orcid":null},"institutions":[{"id":"https://openalex.org/I80693520","display_name":"American University in Cairo","ror":"https://ror.org/0176yqn58","country_code":"EG","type":"education","lineage":["https://openalex.org/I80693520"]},{"id":"https://openalex.org/I207547235","display_name":"Benha University","ror":"https://ror.org/03tn5ee41","country_code":"EG","type":"education","lineage":["https://openalex.org/I207547235"]}],"countries":["EG"],"is_corresponding":true,"raw_author_name":"Eslam Yahya","raw_affiliation_strings":["Center of Nanoelectronics and Devices (CND), American University in Cairo, Egypt","Faculty of Engineering, Benha University, Benha, Egypt"],"affiliations":[{"raw_affiliation_string":"Center of Nanoelectronics and Devices (CND), American University in Cairo, Egypt","institution_ids":["https://openalex.org/I80693520"]},{"raw_affiliation_string":"Faculty of Engineering, Benha University, Benha, Egypt","institution_ids":["https://openalex.org/I207547235"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5063078984","display_name":"H. Zakaria","orcid":"https://orcid.org/0000-0002-2713-5437"},"institutions":[{"id":"https://openalex.org/I207547235","display_name":"Benha University","ror":"https://ror.org/03tn5ee41","country_code":"EG","type":"education","lineage":["https://openalex.org/I207547235"]}],"countries":["EG"],"is_corresponding":false,"raw_author_name":"Hatem Zakaria","raw_affiliation_strings":["Faculty of Engineering, Benha University, Benha, Egypt"],"affiliations":[{"raw_affiliation_string":"Faculty of Engineering, Benha University, Benha, Egypt","institution_ids":["https://openalex.org/I207547235"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5084980840","display_name":"Yehea Ismail","orcid":"https://orcid.org/0000-0003-3956-7533"},"institutions":[{"id":"https://openalex.org/I80693520","display_name":"American University in Cairo","ror":"https://ror.org/0176yqn58","country_code":"EG","type":"education","lineage":["https://openalex.org/I80693520"]}],"countries":["EG"],"is_corresponding":false,"raw_author_name":"Yehea Ismail","raw_affiliation_strings":["Center of Nanoelectronics and Devices (CND), American University in Cairo, Egypt"],"affiliations":[{"raw_affiliation_string":"Center of Nanoelectronics and Devices (CND), American University in Cairo, Egypt","institution_ids":["https://openalex.org/I80693520"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5084741373"],"corresponding_institution_ids":["https://openalex.org/I207547235","https://openalex.org/I80693520"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.14720032,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":93},"biblio":{"volume":null,"issue":null,"first_page":"596","last_page":"600"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8088212013244629},{"id":"https://openalex.org/keywords/deadlock-prevention-algorithms","display_name":"Deadlock prevention algorithms","score":0.776827871799469},{"id":"https://openalex.org/keywords/asynchronous-communication","display_name":"Asynchronous communication","score":0.7285876274108887},{"id":"https://openalex.org/keywords/deadlock","display_name":"Deadlock","score":0.7197996377944946},{"id":"https://openalex.org/keywords/merge","display_name":"Merge (version control)","score":0.6468443870544434},{"id":"https://openalex.org/keywords/selection","display_name":"Selection (genetic algorithm)","score":0.5204116106033325},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5037350058555603},{"id":"https://openalex.org/keywords/verilog","display_name":"Verilog","score":0.4899222254753113},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.3901817202568054},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.3350658714771271},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.15453416109085083},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.11627733707427979},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.09081658720970154}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8088212013244629},{"id":"https://openalex.org/C113429609","wikidata":"https://www.wikidata.org/wiki/Q4060699","display_name":"Deadlock prevention algorithms","level":3,"score":0.776827871799469},{"id":"https://openalex.org/C151319957","wikidata":"https://www.wikidata.org/wiki/Q752739","display_name":"Asynchronous communication","level":2,"score":0.7285876274108887},{"id":"https://openalex.org/C159023740","wikidata":"https://www.wikidata.org/wiki/Q623276","display_name":"Deadlock","level":2,"score":0.7197996377944946},{"id":"https://openalex.org/C197129107","wikidata":"https://www.wikidata.org/wiki/Q1921621","display_name":"Merge (version control)","level":2,"score":0.6468443870544434},{"id":"https://openalex.org/C81917197","wikidata":"https://www.wikidata.org/wiki/Q628760","display_name":"Selection (genetic algorithm)","level":2,"score":0.5204116106033325},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5037350058555603},{"id":"https://openalex.org/C2779030575","wikidata":"https://www.wikidata.org/wiki/Q827773","display_name":"Verilog","level":3,"score":0.4899222254753113},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3901817202568054},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.3350658714771271},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.15453416109085083},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.11627733707427979},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.09081658720970154},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/icecs.2015.7440387","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecs.2015.7440387","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":11,"referenced_works":["https://openalex.org/W16511050","https://openalex.org/W232434517","https://openalex.org/W1991801986","https://openalex.org/W2087554268","https://openalex.org/W2102495626","https://openalex.org/W2123196056","https://openalex.org/W2138215210","https://openalex.org/W2165873073","https://openalex.org/W2487142227","https://openalex.org/W3152284992","https://openalex.org/W6600687751"],"related_works":["https://openalex.org/W2050076411","https://openalex.org/W2001478969","https://openalex.org/W1542183432","https://openalex.org/W2360686363","https://openalex.org/W1900787600","https://openalex.org/W2136552483","https://openalex.org/W2117224408","https://openalex.org/W2166954426","https://openalex.org/W3137070212","https://openalex.org/W2379911191"],"abstract_inverted_index":{"In":[0],"this":[1],"paper":[2],"we":[3],"introduce":[4],"an":[5],"algorithm":[6,40,65],"that":[7],"detects":[8,41],"the":[9,16,24,30,39,42,45,49,61],"deadlock":[10,50],"in":[11,26],"conditional":[12],"asynchronous":[13],"circuits":[14],"when":[15],"selection":[17,32],"controls":[18],"are":[19],"not":[20],"matched.":[21],"By":[22],"knowing":[23],"slack":[25,56],"each":[27,35],"branch":[28,46],"and":[29,37,52,68],"detailed":[31],"pattern":[33],"for":[34],"Split":[36],"Merge,":[38],"deadlock,":[43],"specifies":[44],"at":[47],"which":[48],"occurs,":[51],"determines":[53],"how":[54],"much":[55],"is":[57,66],"needed":[58],"to":[59],"free":[60],"deadlock.":[62],"The":[63],"proposed":[64],"implemented":[67],"tested":[69],"against":[70],"Verilog":[71],"simulation.":[72]},"counts_by_year":[{"year":2021,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}