{"id":"https://openalex.org/W2311658056","doi":"https://doi.org/10.1109/icecs.2015.7440377","title":"A scalable synchronous reload technique for wide division range multi modulus dividers","display_name":"A scalable synchronous reload technique for wide division range multi modulus dividers","publication_year":2015,"publication_date":"2015-12-01","ids":{"openalex":"https://openalex.org/W2311658056","doi":"https://doi.org/10.1109/icecs.2015.7440377","mag":"2311658056"},"language":"en","primary_location":{"id":"doi:10.1109/icecs.2015.7440377","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecs.2015.7440377","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5013283394","display_name":"Mohammed El\u2010Shennawy","orcid":null},"institutions":[{"id":"https://openalex.org/I78650965","display_name":"Technische Universit\u00e4t Dresden","ror":"https://ror.org/042aqky30","country_code":"DE","type":"education","lineage":["https://openalex.org/I78650965"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Mohammed El-Shennawy","raw_affiliation_strings":["Chair for Circuit Design and Network Theory, Technische Universit\u00e4t Dresden, Dresden, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Chair for Circuit Design and Network Theory, Technische Universit\u00e4t Dresden, Dresden, Germany","institution_ids":["https://openalex.org/I78650965"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5037911538","display_name":"Mohamed Hussein Eissa","orcid":"https://orcid.org/0000-0001-6232-6979"},"institutions":[{"id":"https://openalex.org/I92894754","display_name":"Leibniz Institute for High Performance Microelectronics","ror":"https://ror.org/0489gab80","country_code":"DE","type":"facility","lineage":["https://openalex.org/I315704651","https://openalex.org/I92894754"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Mohamed Eissa","raw_affiliation_strings":["IHP Microelectronics, Frankfurt Oder, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"IHP Microelectronics, Frankfurt Oder, Germany","institution_ids":["https://openalex.org/I92894754"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5063368409","display_name":"Markus Schulz","orcid":null},"institutions":[{"id":"https://openalex.org/I78650965","display_name":"Technische Universit\u00e4t Dresden","ror":"https://ror.org/042aqky30","country_code":"DE","type":"education","lineage":["https://openalex.org/I78650965"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Markus Schulz","raw_affiliation_strings":["Chair for Circuit Design and Network Theory, Technische Universit\u00e4t Dresden, Dresden, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Chair for Circuit Design and Network Theory, Technische Universit\u00e4t Dresden, Dresden, Germany","institution_ids":["https://openalex.org/I78650965"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5065330603","display_name":"Niko Joram","orcid":"https://orcid.org/0000-0003-1621-1876"},"institutions":[{"id":"https://openalex.org/I78650965","display_name":"Technische Universit\u00e4t Dresden","ror":"https://ror.org/042aqky30","country_code":"DE","type":"education","lineage":["https://openalex.org/I78650965"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Niko Joram","raw_affiliation_strings":["Chair for Circuit Design and Network Theory, Technische Universit\u00e4t Dresden, Dresden, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Chair for Circuit Design and Network Theory, Technische Universit\u00e4t Dresden, Dresden, Germany","institution_ids":["https://openalex.org/I78650965"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5049816054","display_name":"Frank Ellinger","orcid":"https://orcid.org/0000-0001-6714-0479"},"institutions":[{"id":"https://openalex.org/I78650965","display_name":"Technische Universit\u00e4t Dresden","ror":"https://ror.org/042aqky30","country_code":"DE","type":"education","lineage":["https://openalex.org/I78650965"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Frank Ellinger","raw_affiliation_strings":["Chair for Circuit Design and Network Theory, Technische Universit\u00e4t Dresden, Dresden, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Chair for Circuit Design and Network Theory, Technische Universit\u00e4t Dresden, Dresden, Germany","institution_ids":["https://openalex.org/I78650965"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.6025,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.74313901,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"555","last_page":"558"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9968000054359436,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11444","display_name":"Electromagnetic Compatibility and Noise Suppression","score":0.9957000017166138,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/division","display_name":"Division (mathematics)","score":0.6992887258529663},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5665448307991028},{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"Phase-locked loop","score":0.5358428359031677},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.525311291217804},{"id":"https://openalex.org/keywords/frequency-divider","display_name":"Frequency divider","score":0.5124835968017578},{"id":"https://openalex.org/keywords/range","display_name":"Range (aeronautics)","score":0.5083381533622742},{"id":"https://openalex.org/keywords/lock","display_name":"Lock (firearm)","score":0.48674583435058594},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.47700002789497375},{"id":"https://openalex.org/keywords/integer","display_name":"Integer (computer science)","score":0.47504568099975586},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.45364663004875183},{"id":"https://openalex.org/keywords/modulus","display_name":"Modulus","score":0.4355800449848175},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.2943914532661438},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.24775686860084534},{"id":"https://openalex.org/keywords/phase-noise","display_name":"Phase noise","score":0.24645009636878967},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.0898369550704956},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.08955144882202148},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.08772173523902893}],"concepts":[{"id":"https://openalex.org/C60798267","wikidata":"https://www.wikidata.org/wiki/Q1226939","display_name":"Division (mathematics)","level":2,"score":0.6992887258529663},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5665448307991028},{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.5358428359031677},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.525311291217804},{"id":"https://openalex.org/C74982907","wikidata":"https://www.wikidata.org/wiki/Q1455624","display_name":"Frequency divider","level":3,"score":0.5124835968017578},{"id":"https://openalex.org/C204323151","wikidata":"https://www.wikidata.org/wiki/Q905424","display_name":"Range (aeronautics)","level":2,"score":0.5083381533622742},{"id":"https://openalex.org/C174839445","wikidata":"https://www.wikidata.org/wiki/Q1134386","display_name":"Lock (firearm)","level":2,"score":0.48674583435058594},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.47700002789497375},{"id":"https://openalex.org/C97137487","wikidata":"https://www.wikidata.org/wiki/Q729138","display_name":"Integer (computer science)","level":2,"score":0.47504568099975586},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.45364663004875183},{"id":"https://openalex.org/C193867417","wikidata":"https://www.wikidata.org/wiki/Q6889814","display_name":"Modulus","level":2,"score":0.4355800449848175},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.2943914532661438},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.24775686860084534},{"id":"https://openalex.org/C89631360","wikidata":"https://www.wikidata.org/wiki/Q1428766","display_name":"Phase noise","level":2,"score":0.24645009636878967},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.0898369550704956},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.08955144882202148},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.08772173523902893},{"id":"https://openalex.org/C77088390","wikidata":"https://www.wikidata.org/wiki/Q8513","display_name":"Database","level":1,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C146978453","wikidata":"https://www.wikidata.org/wiki/Q3798668","display_name":"Aerospace engineering","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/icecs.2015.7440377","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecs.2015.7440377","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.8899999856948853,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W1508467339","https://openalex.org/W2026991756","https://openalex.org/W2057759113","https://openalex.org/W2082266173","https://openalex.org/W2099990255","https://openalex.org/W2137782631","https://openalex.org/W2139309588","https://openalex.org/W2139625690","https://openalex.org/W2153369292","https://openalex.org/W2538546762","https://openalex.org/W4248972354","https://openalex.org/W6682357739"],"related_works":["https://openalex.org/W1576949837","https://openalex.org/W2097523295","https://openalex.org/W4360861688","https://openalex.org/W3134930219","https://openalex.org/W984417604","https://openalex.org/W2967785526","https://openalex.org/W2936029881","https://openalex.org/W2072077388","https://openalex.org/W2347235883","https://openalex.org/W2017031079"],"abstract_inverted_index":{"This":[0],"work":[1],"presents":[2],"a":[3,69],"detailed":[4],"study":[5],"for":[6,94],"the":[7,55,81,84,89],"logic":[8],"of":[9,83],"multi":[10],"modulus":[11,17],"frequency":[12],"dividers":[13],"(MMDs)":[14],"with":[15],"multiple":[16],"extensions.":[18],"These":[19],"MMDs":[20,38],"have":[21],"higher":[22],"power":[23],"efficiency":[24],"compared":[25],"to":[26,57,80,88],"conventional":[27],"pulse":[28],"swallow":[29],"dividers.":[30],"In":[31,47,66],"integer-N":[32],"phase":[33],"locked":[34],"loops":[35],"(PLLs),":[36],"these":[37],"are":[39],"fully":[40],"functional":[41],"over":[42],"their":[43],"entire":[44],"division":[45,52],"range.":[46],"fractional-N":[48,95],"PLLs":[49],"however,":[50],"certain":[51],"ratios":[53],"cause":[54],"PLL":[56],"lose":[58],"lock":[59],"which":[60,78],"makes":[61],"multi-standard":[62],"designs":[63],"more":[64],"challenging.":[65],"this":[67,74],"work,":[68],"generic":[70],"scheme":[71],"that":[72],"mitigates":[73],"issue":[75],"is":[76],"proposed":[77],"according":[79],"best":[82],"authors'":[85],"knowledge":[86],"leads":[87],"simplest":[90],"truly-continuous":[91],"wide-division-range":[92],"MMD":[93],"PLLs.":[96]},"counts_by_year":[{"year":2021,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2016,"cited_by_count":2}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}
