{"id":"https://openalex.org/W2309111246","doi":"https://doi.org/10.1109/icecs.2015.7440269","title":"Automatic circuit generation for sequential logic debug","display_name":"Automatic circuit generation for sequential logic debug","publication_year":2015,"publication_date":"2015-12-01","ids":{"openalex":"https://openalex.org/W2309111246","doi":"https://doi.org/10.1109/icecs.2015.7440269","mag":"2309111246"},"language":"en","primary_location":{"id":"doi:10.1109/icecs.2015.7440269","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecs.2015.7440269","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5080128753","display_name":"Helder H. Avelar","orcid":null},"institutions":[{"id":"https://openalex.org/I126460647","display_name":"Universidade Federal do Rio Grande","ror":"https://ror.org/05hpfkn88","country_code":"BR","type":"education","lineage":["https://openalex.org/I126460647"]},{"id":"https://openalex.org/I4388482696","display_name":"Naval Research Laboratory Information Technology Division","ror":"https://ror.org/04xfp8b22","country_code":null,"type":"facility","lineage":["https://openalex.org/I1288214837","https://openalex.org/I1330347796","https://openalex.org/I175003984","https://openalex.org/I3130687028","https://openalex.org/I4388482696"]}],"countries":["BR"],"is_corresponding":true,"raw_author_name":"Helder H. Avelar","raw_affiliation_strings":["Universidade Federal do Rio Grande - FURG, Center for Computational Science - C3"],"affiliations":[{"raw_affiliation_string":"Universidade Federal do Rio Grande - FURG, Center for Computational Science - C3","institution_ids":["https://openalex.org/I126460647","https://openalex.org/I4388482696"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5062131940","display_name":"Paulo F. Butzen","orcid":"https://orcid.org/0000-0003-1587-7596"},"institutions":[{"id":"https://openalex.org/I4388482696","display_name":"Naval Research Laboratory Information Technology Division","ror":"https://ror.org/04xfp8b22","country_code":null,"type":"facility","lineage":["https://openalex.org/I1288214837","https://openalex.org/I1330347796","https://openalex.org/I175003984","https://openalex.org/I3130687028","https://openalex.org/I4388482696"]},{"id":"https://openalex.org/I126460647","display_name":"Universidade Federal do Rio Grande","ror":"https://ror.org/05hpfkn88","country_code":"BR","type":"education","lineage":["https://openalex.org/I126460647"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Paulo F. Butzen","raw_affiliation_strings":["Universidade Federal do Rio Grande - FURG, Center for Computational Science - C3"],"affiliations":[{"raw_affiliation_string":"Universidade Federal do Rio Grande - FURG, Center for Computational Science - C3","institution_ids":["https://openalex.org/I126460647","https://openalex.org/I4388482696"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5090563366","display_name":"Renato P. Ribas","orcid":"https://orcid.org/0000-0002-9895-7489"},"institutions":[{"id":"https://openalex.org/I130442723","display_name":"Universidade Federal do Rio Grande do Sul","ror":"https://ror.org/041yk2d64","country_code":"BR","type":"education","lineage":["https://openalex.org/I130442723"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Renato P. Ribas","raw_affiliation_strings":["Universidade Federal do Rio Grande do Sul-UFRGS, Instituto de Inform\u00e1tica"],"affiliations":[{"raw_affiliation_string":"Universidade Federal do Rio Grande do Sul-UFRGS, Instituto de Inform\u00e1tica","institution_ids":["https://openalex.org/I130442723"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5080128753"],"corresponding_institution_ids":["https://openalex.org/I126460647","https://openalex.org/I4388482696"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.16453601,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"141","last_page":"144"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12122","display_name":"Physical Unclonable Functions (PUFs) and Hardware Security","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/debugging","display_name":"Debugging","score":0.6884287595748901},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6814216375350952},{"id":"https://openalex.org/keywords/sequential-logic","display_name":"Sequential logic","score":0.6002240180969238},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.5942732691764832},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.5094416737556458},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.47019967436790466},{"id":"https://openalex.org/keywords/logic-optimization","display_name":"Logic optimization","score":0.46480146050453186},{"id":"https://openalex.org/keywords/pass-transistor-logic","display_name":"Pass transistor logic","score":0.4445610046386719},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.41489285230636597},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4072643518447876},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.40719643235206604},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.39234206080436707},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.3773896396160126},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3248433470726013},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.27215245366096497},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.22440364956855774},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2229389250278473},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.1745513677597046},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.10536864399909973}],"concepts":[{"id":"https://openalex.org/C168065819","wikidata":"https://www.wikidata.org/wiki/Q845566","display_name":"Debugging","level":2,"score":0.6884287595748901},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6814216375350952},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.6002240180969238},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.5942732691764832},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.5094416737556458},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.47019967436790466},{"id":"https://openalex.org/C28449271","wikidata":"https://www.wikidata.org/wiki/Q6667469","display_name":"Logic optimization","level":4,"score":0.46480146050453186},{"id":"https://openalex.org/C198521697","wikidata":"https://www.wikidata.org/wiki/Q7142438","display_name":"Pass transistor logic","level":4,"score":0.4445610046386719},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.41489285230636597},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4072643518447876},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.40719643235206604},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.39234206080436707},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3773896396160126},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3248433470726013},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.27215245366096497},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.22440364956855774},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2229389250278473},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.1745513677597046},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.10536864399909973},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/icecs.2015.7440269","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecs.2015.7440269","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W197859044","https://openalex.org/W1518236483","https://openalex.org/W1592908851","https://openalex.org/W1974974397","https://openalex.org/W2034476614","https://openalex.org/W2116376248","https://openalex.org/W2137176071","https://openalex.org/W2148960378","https://openalex.org/W3103339143","https://openalex.org/W6608021008"],"related_works":["https://openalex.org/W3129977055","https://openalex.org/W1966764473","https://openalex.org/W1553855433","https://openalex.org/W1488117239","https://openalex.org/W2386022279","https://openalex.org/W2098419840","https://openalex.org/W2152533674","https://openalex.org/W2991771859","https://openalex.org/W2006855068","https://openalex.org/W2356714888"],"abstract_inverted_index":{"Integrated":[0],"circuits":[1,107],"(ICs)":[2],"evolution":[3],"follows":[4],"a":[5,68],"complex":[6],"scaling":[7],"process":[8],"and":[9,28,55,86,92,111,114,124],"an":[10,34],"increasing":[11],"number":[12],"of":[13,44,58,73,80,103],"transistors":[14],"per":[15],"chip.":[16],"As":[17],"feature":[18],"sizes":[19],"reduces,":[20],"logic":[21,46],"gates":[22],"get":[23],"more":[24],"susceptible":[25],"to":[26,51,119],"manufacturing":[27],"specification":[29],"errors,":[30],"which":[31],"makes":[32],"testing":[33],"important":[35,50],"step":[36],"in":[37,60],"their":[38],"design.":[39],"The":[40,98],"early":[41],"on-silicon":[42],"validation":[43,106],"the":[45,53,56,101,104,121],"functionality":[47],"is":[48],"very":[49],"reduce":[52],"time-to-market":[54],"cost":[57],"faults":[59,94],"new":[61],"standard":[62],"cell":[63],"libraries.":[64],"This":[65],"paper":[66],"presents":[67],"procedure":[69],"for":[70,76,108],"automatic":[71],"generation":[72],"on-chip":[74],"self-testers":[75],"complete":[77],"logical":[78],"debug":[79],"any":[81],"sequential":[82],"gate.":[83],"All":[84],"shorted":[85],"open":[87],"interconnects,":[88],"short-to-power,":[89],"short-to-ground,":[90],"stuck-open,":[91],"stuck-on":[93],"can":[95],"be":[96],"detected.":[97],"analysis":[99],"compares":[100],"complexity":[102],"generated":[105],"different":[109],"latches":[110],"flip-flops.":[112],"Logic":[113],"physical":[115],"synthesis":[116],"were":[117],"performed":[118],"generate":[120],"circuit":[122],"layouts":[123],"confirm":[125],"its":[126],"practical":[127],"usability.":[128]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}