{"id":"https://openalex.org/W2309094582","doi":"https://doi.org/10.1109/icecs.2015.7440261","title":"An alternative to CMOS stacks based on a floating-gate transistor","display_name":"An alternative to CMOS stacks based on a floating-gate transistor","publication_year":2015,"publication_date":"2015-12-01","ids":{"openalex":"https://openalex.org/W2309094582","doi":"https://doi.org/10.1109/icecs.2015.7440261","mag":"2309094582"},"language":"en","primary_location":{"id":"doi:10.1109/icecs.2015.7440261","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecs.2015.7440261","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5047023966","display_name":"Sherif M. Sharroush","orcid":"https://orcid.org/0000-0001-7911-2571"},"institutions":[{"id":"https://openalex.org/I88017793","display_name":"Port Said University","ror":"https://ror.org/01vx5yq44","country_code":"EG","type":"education","lineage":["https://openalex.org/I88017793"]}],"countries":["EG"],"is_corresponding":true,"raw_author_name":"Sherif M. Sharroush","raw_affiliation_strings":["Dept. of Electrical Engineering Fac. of Engineering, Port Said Univ. Port Said, Egypt"],"affiliations":[{"raw_affiliation_string":"Dept. of Electrical Engineering Fac. of Engineering, Port Said Univ. Port Said, Egypt","institution_ids":["https://openalex.org/I88017793"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5047023966"],"corresponding_institution_ids":["https://openalex.org/I88017793"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.14408619,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"4","issue":null,"first_page":"109","last_page":"112"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/pmos-logic","display_name":"PMOS logic","score":0.8803725838661194},{"id":"https://openalex.org/keywords/nmos-logic","display_name":"NMOS logic","score":0.865754246711731},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.8497835397720337},{"id":"https://openalex.org/keywords/resistor","display_name":"Resistor","score":0.759827196598053},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.6456987261772156},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.6180757880210876},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4939742684364319},{"id":"https://openalex.org/keywords/power\u2013delay-product","display_name":"Power\u2013delay product","score":0.4702405333518982},{"id":"https://openalex.org/keywords/mosfet","display_name":"MOSFET","score":0.4323037564754486},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.41184598207473755},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.39011818170547485},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.37470221519470215}],"concepts":[{"id":"https://openalex.org/C27050352","wikidata":"https://www.wikidata.org/wiki/Q173605","display_name":"PMOS logic","level":4,"score":0.8803725838661194},{"id":"https://openalex.org/C197162436","wikidata":"https://www.wikidata.org/wiki/Q83908","display_name":"NMOS logic","level":4,"score":0.865754246711731},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.8497835397720337},{"id":"https://openalex.org/C137488568","wikidata":"https://www.wikidata.org/wiki/Q5321","display_name":"Resistor","level":3,"score":0.759827196598053},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.6456987261772156},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.6180757880210876},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4939742684364319},{"id":"https://openalex.org/C2776391166","wikidata":"https://www.wikidata.org/wiki/Q7236873","display_name":"Power\u2013delay product","level":4,"score":0.4702405333518982},{"id":"https://openalex.org/C2778413303","wikidata":"https://www.wikidata.org/wiki/Q210793","display_name":"MOSFET","level":4,"score":0.4323037564754486},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.41184598207473755},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.39011818170547485},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.37470221519470215}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/icecs.2015.7440261","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecs.2015.7440261","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.8899999856948853,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":9,"referenced_works":["https://openalex.org/W1518236483","https://openalex.org/W1605344608","https://openalex.org/W2039800769","https://openalex.org/W2100379261","https://openalex.org/W2106237093","https://openalex.org/W2113996606","https://openalex.org/W2160142098","https://openalex.org/W2257517420","https://openalex.org/W3203011645"],"related_works":["https://openalex.org/W4386261925","https://openalex.org/W2048420745","https://openalex.org/W2082944690","https://openalex.org/W2263373136","https://openalex.org/W1914349328","https://openalex.org/W2160067645","https://openalex.org/W2023334077","https://openalex.org/W2005494397","https://openalex.org/W2104885411","https://openalex.org/W1742453416"],"abstract_inverted_index":{"Complementary":[0],"metal-oxide":[1],"semiconductor":[2],"(CMOS)":[3],"circuits":[4],"with":[5,94],"wide":[6],"fan":[7],"in":[8],"certainly":[9],"suffers":[10],"from":[11],"the":[12,18,80,89,110,113,123,126],"relatively":[13],"slow":[14],"response":[15],"due":[16],"to":[17,36,79],"N-channel":[19],"(NMOS)":[20],"or":[21],"P-channel":[22],"(PMOS)":[23],"stack.":[24],"In":[25],"this":[26],"paper,":[27],"a":[28,49,54,69,95],"novel":[29],"circuit":[30],"that":[31,52],"acts":[32],"as":[33,57],"an":[34,105,118],"alternative":[35],"CMOS":[37,92],"stacks":[38],"will":[39,85],"be":[40,86],"presented.":[41],"The":[42,82,101],"proposed":[43,83,102],"scheme":[44,84,103],"is":[45,66],"based":[46],"on":[47],"using":[48,88],"voltage":[50,97],"divider":[51],"has":[53],"variable":[55,64],"resistor":[56,65],"one":[58],"of":[59,98,112,125],"its":[60],"two":[61],"resistors.":[62],"This":[63],"nothing":[67],"but":[68],"floating-gate":[70],"MOS":[71],"transistor":[72],"(FGMOS)":[73],"whose":[74],"control":[75],"gates":[76],"are":[77],"connected":[78],"inputs.":[81],"simulated":[87],"45":[90],"nm":[91],"technology":[93],"power-supply":[96],"1":[99],"V.":[100],"shows":[104],"average":[106],"time-delay":[107],"saving":[108,121],"when":[109,122],"number":[111,124],"inputs":[114,127],"exceeds":[115,128],"4":[116],"and":[117],"energy-delay":[119],"product":[120],"7.":[129]},"counts_by_year":[{"year":2022,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}