{"id":"https://openalex.org/W2059871731","doi":"https://doi.org/10.1109/icecs.2014.7050011","title":"TDES cryptography algorithm acceleration using a reconfigurable functional unit","display_name":"TDES cryptography algorithm acceleration using a reconfigurable functional unit","publication_year":2014,"publication_date":"2014-12-01","ids":{"openalex":"https://openalex.org/W2059871731","doi":"https://doi.org/10.1109/icecs.2014.7050011","mag":"2059871731"},"language":"en","primary_location":{"id":"doi:10.1109/icecs.2014.7050011","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecs.2014.7050011","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5028297120","display_name":"G.C. Cardarilli","orcid":"https://orcid.org/0000-0002-7444-876X"},"institutions":[{"id":"https://openalex.org/I116067653","display_name":"University of Rome Tor Vergata","ror":"https://ror.org/02p77k626","country_code":"IT","type":"education","lineage":["https://openalex.org/I116067653"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"G. C. Cardarilli","raw_affiliation_strings":["Department of Electronic Engineering, University of Rome Tor Vergata, Rome, Italy","Dept. of Electronic Engineering, University of Rome Tor Vergata, Via del Politecnico 1, 00133 Rome, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronic Engineering, University of Rome Tor Vergata, Rome, Italy","institution_ids":["https://openalex.org/I116067653"]},{"raw_affiliation_string":"Dept. of Electronic Engineering, University of Rome Tor Vergata, Via del Politecnico 1, 00133 Rome, Italy","institution_ids":["https://openalex.org/I116067653"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5063300969","display_name":"Luca Di Nunzio","orcid":"https://orcid.org/0000-0002-4312-7939"},"institutions":[{"id":"https://openalex.org/I116067653","display_name":"University of Rome Tor Vergata","ror":"https://ror.org/02p77k626","country_code":"IT","type":"education","lineage":["https://openalex.org/I116067653"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"L. Di Nunzio","raw_affiliation_strings":["Department of Electronic Engineering, University of Rome Tor Vergata, Rome, Italy","Dept. of Electronic Engineering, University of Rome Tor Vergata, Via del Politecnico 1, 00133 Rome, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronic Engineering, University of Rome Tor Vergata, Rome, Italy","institution_ids":["https://openalex.org/I116067653"]},{"raw_affiliation_string":"Dept. of Electronic Engineering, University of Rome Tor Vergata, Via del Politecnico 1, 00133 Rome, Italy","institution_ids":["https://openalex.org/I116067653"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5048482308","display_name":"Rocco Fazzolari","orcid":"https://orcid.org/0000-0002-7383-2663"},"institutions":[{"id":"https://openalex.org/I116067653","display_name":"University of Rome Tor Vergata","ror":"https://ror.org/02p77k626","country_code":"IT","type":"education","lineage":["https://openalex.org/I116067653"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"R. Fazzolari","raw_affiliation_strings":["Department of Electronic Engineering, University of Rome Tor Vergata, Rome, Italy","Dept. of Electronic Engineering, University of Rome Tor Vergata, Via del Politecnico 1, 00133 Rome, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronic Engineering, University of Rome Tor Vergata, Rome, Italy","institution_ids":["https://openalex.org/I116067653"]},{"raw_affiliation_string":"Dept. of Electronic Engineering, University of Rome Tor Vergata, Via del Politecnico 1, 00133 Rome, Italy","institution_ids":["https://openalex.org/I116067653"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5000963583","display_name":"M. Re","orcid":"https://orcid.org/0000-0001-9046-1318"},"institutions":[{"id":"https://openalex.org/I116067653","display_name":"University of Rome Tor Vergata","ror":"https://ror.org/02p77k626","country_code":"IT","type":"education","lineage":["https://openalex.org/I116067653"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"M. Re","raw_affiliation_strings":["Department of Electronic Engineering, University of Rome Tor Vergata, Rome, Italy","Dept. of Electronic Engineering, University of Rome Tor Vergata, Via del Politecnico 1, 00133 Rome, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronic Engineering, University of Rome Tor Vergata, Rome, Italy","institution_ids":["https://openalex.org/I116067653"]},{"raw_affiliation_string":"Dept. of Electronic Engineering, University of Rome Tor Vergata, Via del Politecnico 1, 00133 Rome, Italy","institution_ids":["https://openalex.org/I116067653"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I116067653"],"apc_list":null,"apc_paid":null,"fwci":0.6042,"has_fulltext":false,"cited_by_count":15,"citation_normalized_percentile":{"value":0.61435228,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"419","last_page":"422"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10951","display_name":"Cryptographic Implementations and Security","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9972000122070312,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8101108074188232},{"id":"https://openalex.org/keywords/nios-ii","display_name":"Nios II","score":0.7878837585449219},{"id":"https://openalex.org/keywords/vhdl","display_name":"VHDL","score":0.7053546905517578},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6211212873458862},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5700469017028809},{"id":"https://openalex.org/keywords/microprocessor","display_name":"Microprocessor","score":0.5389708876609802},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.497060090303421},{"id":"https://openalex.org/keywords/stratix","display_name":"Stratix","score":0.49600085616111755},{"id":"https://openalex.org/keywords/hardware-description-language","display_name":"Hardware description language","score":0.49198219180107117},{"id":"https://openalex.org/keywords/cryptography","display_name":"Cryptography","score":0.45057517290115356},{"id":"https://openalex.org/keywords/encryption","display_name":"Encryption","score":0.4294377863407135},{"id":"https://openalex.org/keywords/hardware-acceleration","display_name":"Hardware acceleration","score":0.4215032458305359},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.3944544792175293},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.11425206065177917}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8101108074188232},{"id":"https://openalex.org/C2781190120","wikidata":"https://www.wikidata.org/wiki/Q438281","display_name":"Nios II","level":3,"score":0.7878837585449219},{"id":"https://openalex.org/C36941000","wikidata":"https://www.wikidata.org/wiki/Q209455","display_name":"VHDL","level":3,"score":0.7053546905517578},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6211212873458862},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5700469017028809},{"id":"https://openalex.org/C2780728072","wikidata":"https://www.wikidata.org/wiki/Q5297","display_name":"Microprocessor","level":2,"score":0.5389708876609802},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.497060090303421},{"id":"https://openalex.org/C2776277307","wikidata":"https://www.wikidata.org/wiki/Q22074755","display_name":"Stratix","level":3,"score":0.49600085616111755},{"id":"https://openalex.org/C42143788","wikidata":"https://www.wikidata.org/wiki/Q173341","display_name":"Hardware description language","level":3,"score":0.49198219180107117},{"id":"https://openalex.org/C178489894","wikidata":"https://www.wikidata.org/wiki/Q8789","display_name":"Cryptography","level":2,"score":0.45057517290115356},{"id":"https://openalex.org/C148730421","wikidata":"https://www.wikidata.org/wiki/Q141090","display_name":"Encryption","level":2,"score":0.4294377863407135},{"id":"https://openalex.org/C13164978","wikidata":"https://www.wikidata.org/wiki/Q600158","display_name":"Hardware acceleration","level":3,"score":0.4215032458305359},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3944544792175293},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.11425206065177917}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/icecs.2014.7050011","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecs.2014.7050011","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS)","raw_type":"proceedings-article"},{"id":"pmh:oai:art.torvergata.it:2108/242178","is_oa":false,"landing_page_url":"http://hdl.handle.net/2108/242178","pdf_url":null,"source":{"id":"https://openalex.org/S4306400993","display_name":"Cineca Institutional Research Information System (Tor Vergata University)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I116067653","host_organization_name":"University of Rome Tor Vergata","host_organization_lineage":["https://openalex.org/I116067653"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"info:eu-repo/semantics/conferenceObject"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.44999998807907104,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":4,"referenced_works":["https://openalex.org/W1969693240","https://openalex.org/W2107923684","https://openalex.org/W3149144981","https://openalex.org/W6793222508"],"related_works":["https://openalex.org/W2110818533","https://openalex.org/W1917852300","https://openalex.org/W2384838054","https://openalex.org/W2139058049","https://openalex.org/W2548456620","https://openalex.org/W2376018793","https://openalex.org/W2162623979","https://openalex.org/W2911649771","https://openalex.org/W2109992022","https://openalex.org/W3189556868"],"abstract_inverted_index":{"Many":[0],"cryptography":[1],"algorithm":[2,96],"contain":[3],"a":[4,98,107],"lots":[5],"of":[6,17,28,31,39,64,73,82,90,152,160],"data":[7,40],"bit":[8,58],"manipulation":[9,59],"operations.":[10],"Unfortunately,":[11],"the":[12,26,37,57,62,68,79,83,88,137,142,150,153,158,161],"Instruction":[13],"Set":[14],"Architecure":[15],"(ISA)":[16],"general":[18],"purpose":[19],"microprocessors":[20],"is":[21,33,104,149],"usually":[22],"word":[23],"oriented.":[24],"Consequently":[25],"execution":[27,74],"this":[29],"kind":[30],"algorithms":[32,66],"not":[34],"optimized":[35],"and":[36,134],"computation":[38,63],"represented":[41],"by":[42],"single":[43],"bits":[44],"or":[45],"sub-words":[46],"can":[47],"require":[48],"several":[49],"clock":[50],"cycles.":[51],"Reconfigurable":[52,99],"hardware":[53,163],"accelerators":[54],"oriented":[55],"to":[56,157],"could":[60],"accelerate":[61],"these":[65],"increasing":[67],"microprocessor":[69,109],"performance":[70],"in":[71,120],"terms":[72],"time.":[75],"This":[76],"work":[77],"presents":[78],"experimental":[80],"results":[81],"speed-up":[84,154],"factor":[85,155],"obtained":[86],"for":[87],"implementation":[89],"TDES":[91],"(Triple":[92],"Data":[93],"Encryption":[94],"Standard)":[95],"when":[97],"Functional":[100],"Unit":[101],"ADAPTO":[102,117],"[1]":[103],"integrated":[105,135],"with":[106,136],"RISC":[108],"(the":[110],"Altera":[111],"NIOS-II":[112],"soft":[113,139],"processor":[114,140],"[2]).":[115],"The":[116,147],"unit,":[118],"described":[119],"VHDL":[121],"(VHSIC":[122],"Hardware":[123],"Description":[124],"Language),":[125],"has":[126],"been":[127],"implemented":[128],"on":[129],"an":[130],"Altera-Stratix":[131],"II":[132],"FPGA":[133],"Nios":[138],"using":[141],"Custom":[143],"Logic":[144],"feature":[145],"[4].":[146],"objective":[148],"measurement":[151],"related":[156],"introduction":[159],"reconfigurable":[162],"accelerator.":[164]},"counts_by_year":[{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":2},{"year":2019,"cited_by_count":2},{"year":2018,"cited_by_count":6},{"year":2017,"cited_by_count":3}],"updated_date":"2026-08-12T21:12:35.861297","created_date":"2025-10-10T00:00:00"}
