{"id":"https://openalex.org/W1963805795","doi":"https://doi.org/10.1109/icecs.2013.6815569","title":"Netlist partitioning method suitable for adaptive computing systems","display_name":"Netlist partitioning method suitable for adaptive computing systems","publication_year":2013,"publication_date":"2013-12-01","ids":{"openalex":"https://openalex.org/W1963805795","doi":"https://doi.org/10.1109/icecs.2013.6815569","mag":"1963805795"},"language":"en","primary_location":{"id":"doi:10.1109/icecs.2013.6815569","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecs.2013.6815569","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5031738295","display_name":"Nabil Kerkiz","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Nabil F. Kerkiz","raw_affiliation_strings":["Intel Corporation, Austin, Texas, USA","Intel Corporation, Austin, Texas, USA#TAB#"],"affiliations":[{"raw_affiliation_string":"Intel Corporation, Austin, Texas, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corporation, Austin, Texas, USA#TAB#","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5022601896","display_name":"Amr Elchouemi","orcid":null},"institutions":[{"id":"https://openalex.org/I2801910015","display_name":"Abu Dhabi Department of Education and Knowledge","ror":"https://ror.org/02x5wtf56","country_code":"AE","type":"government","lineage":["https://openalex.org/I2801910015"]}],"countries":["AE"],"is_corresponding":false,"raw_author_name":"Amr Elchouemi","raw_affiliation_strings":["Abu Dhabi Education Council"],"affiliations":[{"raw_affiliation_string":"Abu Dhabi Education Council","institution_ids":["https://openalex.org/I2801910015"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5031738295"],"corresponding_institution_ids":["https://openalex.org/I1343180700"],"apc_list":null,"apc_paid":null,"fwci":0.3152,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.56905633,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"950","last_page":"953"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/netlist","display_name":"Netlist","score":0.8279033303260803},{"id":"https://openalex.org/keywords/debugging","display_name":"Debugging","score":0.7628932595252991},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7599672675132751},{"id":"https://openalex.org/keywords/champion","display_name":"Champion","score":0.6979029178619385},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6512430906295776},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.5595504641532898},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4571495056152344},{"id":"https://openalex.org/keywords/path","display_name":"Path (computing)","score":0.4453997313976288},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.426724910736084},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.3587875962257385},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.34484773874282837},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3418729901313782},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.10907500982284546}],"concepts":[{"id":"https://openalex.org/C177650935","wikidata":"https://www.wikidata.org/wiki/Q1760303","display_name":"Netlist","level":2,"score":0.8279033303260803},{"id":"https://openalex.org/C168065819","wikidata":"https://www.wikidata.org/wiki/Q845566","display_name":"Debugging","level":2,"score":0.7628932595252991},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7599672675132751},{"id":"https://openalex.org/C2780465443","wikidata":"https://www.wikidata.org/wiki/Q852061","display_name":"Champion","level":2,"score":0.6979029178619385},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6512430906295776},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.5595504641532898},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4571495056152344},{"id":"https://openalex.org/C2777735758","wikidata":"https://www.wikidata.org/wiki/Q817765","display_name":"Path (computing)","level":2,"score":0.4453997313976288},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.426724910736084},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.3587875962257385},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.34484773874282837},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3418729901313782},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.10907500982284546},{"id":"https://openalex.org/C199539241","wikidata":"https://www.wikidata.org/wiki/Q7748","display_name":"Law","level":1,"score":0.0},{"id":"https://openalex.org/C17744445","wikidata":"https://www.wikidata.org/wiki/Q36442","display_name":"Political science","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/icecs.2013.6815569","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecs.2013.6815569","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.5400000214576721,"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W1993682921","https://openalex.org/W2026793883","https://openalex.org/W2086629796","https://openalex.org/W2095117703","https://openalex.org/W2128583835","https://openalex.org/W2153692451","https://openalex.org/W2161455936","https://openalex.org/W2168908452","https://openalex.org/W2518852025","https://openalex.org/W4235310246","https://openalex.org/W4236269389","https://openalex.org/W4253000195"],"related_works":["https://openalex.org/W2170314243","https://openalex.org/W2119179026","https://openalex.org/W2794947590","https://openalex.org/W4243305727","https://openalex.org/W2145339442","https://openalex.org/W3217774925","https://openalex.org/W4386694274","https://openalex.org/W3146543203","https://openalex.org/W2795180100","https://openalex.org/W2099346120"],"abstract_inverted_index":{"Adaptive":[0],"computing":[1],"systems":[2],"(ACSs)":[3],"are":[4],"flexible":[5],"hardware":[6,36],"accelerators":[7],"for":[8,34],"applications":[9,23,61],"in":[10],"domains":[11],"such":[12],"as":[13],"image":[14],"and":[15,40,74,84],"digital":[16],"signal":[17],"processing.":[18],"However,":[19],"the":[20,27,51,57,67],"mapping":[21,59],"of":[22,53,60,70],"onto":[24,62],"ACSs":[25],"using":[26],"traditional":[28],"methods":[29],"can":[30],"take":[31],"long":[32],"time":[33],"a":[35,75],"engineer":[37],"to":[38,55],"develop":[39],"debug.":[41],"A":[42],"software":[43],"design":[44],"environment":[45],"called":[46],"CHAMPION":[47,71],"was":[48],"developed":[49],"at":[50],"University":[52],"Tennessee":[54],"enable":[56],"automated":[58],"ACSs.":[63],"In":[64],"this":[65],"paper":[66],"compilation":[68],"path":[69],"is":[72,87],"described":[73],"new":[76],"recursive":[77],"partitioning":[78,94,101],"method":[79,91],"based":[80],"on":[81],"topological":[82],"ordering":[83],"levelization":[85],"(RPL)":[86],"presented.":[88],"The":[89],"proposed":[90],"performs":[92],"multi-FPGA":[93],"by":[95],"taking":[96],"into":[97],"account":[98],"six":[99],"different":[100],"constraints.":[102]},"counts_by_year":[{"year":2013,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}