{"id":"https://openalex.org/W2012329812","doi":"https://doi.org/10.1109/icecs.2013.6815441","title":"Using body bias when upsizing length for maximizing the static noise margins of CMOS gates","display_name":"Using body bias when upsizing length for maximizing the static noise margins of CMOS gates","publication_year":2013,"publication_date":"2013-12-01","ids":{"openalex":"https://openalex.org/W2012329812","doi":"https://doi.org/10.1109/icecs.2013.6815441","mag":"2012329812"},"language":"en","primary_location":{"id":"doi:10.1109/icecs.2013.6815441","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecs.2013.6815441","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5001440130","display_name":"Fekri Kharbash","orcid":null},"institutions":[{"id":"https://openalex.org/I201726411","display_name":"United Arab Emirates University","ror":"https://ror.org/01km6p862","country_code":"AE","type":"education","lineage":["https://openalex.org/I201726411"]}],"countries":["AE"],"is_corresponding":false,"raw_author_name":"Fekri Kharbash","raw_affiliation_strings":["College of Information Technology, United Arab Emirates University, Al Ain, UAE","College of Information Technology, United Arab Emirates University, PO Box 15551, Al Ain, UAE"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"College of Information Technology, United Arab Emirates University, Al Ain, UAE","institution_ids":["https://openalex.org/I201726411"]},{"raw_affiliation_string":"College of Information Technology, United Arab Emirates University, PO Box 15551, Al Ain, UAE","institution_ids":["https://openalex.org/I201726411"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5103819348","display_name":"Valeriu Beiu","orcid":"https://orcid.org/0000-0001-8185-956X"},"institutions":[{"id":"https://openalex.org/I201726411","display_name":"United Arab Emirates University","ror":"https://ror.org/01km6p862","country_code":"AE","type":"education","lineage":["https://openalex.org/I201726411"]}],"countries":["AE"],"is_corresponding":false,"raw_author_name":"Valeriu Beiu","raw_affiliation_strings":["College of Information Technology, United Arab Emirates University, Al Ain, UAE","College of Information Technology, United Arab Emirates University, PO Box 15551, Al Ain, UAE"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"College of Information Technology, United Arab Emirates University, Al Ain, UAE","institution_ids":["https://openalex.org/I201726411"]},{"raw_affiliation_string":"College of Information Technology, United Arab Emirates University, PO Box 15551, Al Ain, UAE","institution_ids":["https://openalex.org/I201726411"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5035274606","display_name":"Mihai Tache","orcid":null},"institutions":[{"id":"https://openalex.org/I201726411","display_name":"United Arab Emirates University","ror":"https://ror.org/01km6p862","country_code":"AE","type":"education","lineage":["https://openalex.org/I201726411"]}],"countries":["AE"],"is_corresponding":false,"raw_author_name":"Mihai Tache","raw_affiliation_strings":["College of Information Technology, United Arab Emirates University, Al Ain, UAE","College of Information Technology, United Arab Emirates University, PO Box 15551, Al Ain, UAE"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"College of Information Technology, United Arab Emirates University, Al Ain, UAE","institution_ids":["https://openalex.org/I201726411"]},{"raw_affiliation_string":"College of Information Technology, United Arab Emirates University, PO Box 15551, Al Ain, UAE","institution_ids":["https://openalex.org/I201726411"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5027668962","display_name":"Walid Ibrahim","orcid":"https://orcid.org/0000-0003-0102-6950"},"institutions":[{"id":"https://openalex.org/I201726411","display_name":"United Arab Emirates University","ror":"https://ror.org/01km6p862","country_code":"AE","type":"education","lineage":["https://openalex.org/I201726411"]}],"countries":["AE"],"is_corresponding":false,"raw_author_name":"Walid Ibrahim","raw_affiliation_strings":["College of Information Technology, United Arab Emirates University, Al Ain, UAE","College of Information Technology, United Arab Emirates University, PO Box 15551, Al Ain, UAE"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"College of Information Technology, United Arab Emirates University, Al Ain, UAE","institution_ids":["https://openalex.org/I201726411"]},{"raw_affiliation_string":"College of Information Technology, United Arab Emirates University, PO Box 15551, Al Ain, UAE","institution_ids":["https://openalex.org/I201726411"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I201726411"],"apc_list":null,"apc_paid":null,"fwci":0.8106,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.65848268,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":94,"max":96},"biblio":{"volume":"31","issue":null,"first_page":"409","last_page":"412"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/nmos-logic","display_name":"NMOS logic","score":0.7336369752883911},{"id":"https://openalex.org/keywords/pmos-logic","display_name":"PMOS logic","score":0.6974839568138123},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5919538140296936},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.4541863203048706},{"id":"https://openalex.org/keywords/noise","display_name":"Noise (video)","score":0.45126014947891235},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.4479660987854004},{"id":"https://openalex.org/keywords/nand-gate","display_name":"NAND gate","score":0.4255572259426117},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.4237281382083893},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.37494468688964844},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.3723728060722351},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.35557472705841064},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.2576523423194885},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.22355082631111145},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.22223922610282898}],"concepts":[{"id":"https://openalex.org/C197162436","wikidata":"https://www.wikidata.org/wiki/Q83908","display_name":"NMOS logic","level":4,"score":0.7336369752883911},{"id":"https://openalex.org/C27050352","wikidata":"https://www.wikidata.org/wiki/Q173605","display_name":"PMOS logic","level":4,"score":0.6974839568138123},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5919538140296936},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.4541863203048706},{"id":"https://openalex.org/C99498987","wikidata":"https://www.wikidata.org/wiki/Q2210247","display_name":"Noise (video)","level":3,"score":0.45126014947891235},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.4479660987854004},{"id":"https://openalex.org/C124296912","wikidata":"https://www.wikidata.org/wiki/Q575178","display_name":"NAND gate","level":3,"score":0.4255572259426117},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.4237281382083893},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.37494468688964844},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.3723728060722351},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.35557472705841064},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.2576523423194885},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.22355082631111145},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.22223922610282898},{"id":"https://openalex.org/C115961682","wikidata":"https://www.wikidata.org/wiki/Q860623","display_name":"Image (mathematics)","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/icecs.2013.6815441","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecs.2013.6815441","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":30,"referenced_works":["https://openalex.org/W1889226263","https://openalex.org/W1905043939","https://openalex.org/W1966298615","https://openalex.org/W1966879182","https://openalex.org/W2041069167","https://openalex.org/W2044955139","https://openalex.org/W2055857026","https://openalex.org/W2069345435","https://openalex.org/W2084201475","https://openalex.org/W2095816496","https://openalex.org/W2097579177","https://openalex.org/W2101848657","https://openalex.org/W2103341962","https://openalex.org/W2106550461","https://openalex.org/W2108143446","https://openalex.org/W2113631160","https://openalex.org/W2122326937","https://openalex.org/W2125539073","https://openalex.org/W2144154842","https://openalex.org/W2146824752","https://openalex.org/W2148923014","https://openalex.org/W2150526221","https://openalex.org/W2152293406","https://openalex.org/W2156817051","https://openalex.org/W2161648718","https://openalex.org/W2185884025","https://openalex.org/W6639680632","https://openalex.org/W6639877556","https://openalex.org/W6664950366","https://openalex.org/W6682145182"],"related_works":["https://openalex.org/W4386261925","https://openalex.org/W2048420745","https://openalex.org/W2082944690","https://openalex.org/W2263373136","https://openalex.org/W1914349328","https://openalex.org/W2160067645","https://openalex.org/W2023334077","https://openalex.org/W2005494397","https://openalex.org/W2730314563","https://openalex.org/W2058541779"],"abstract_inverted_index":{"This":[0],"paper":[1,68],"uses":[2],"body":[3],"bias":[4],"for":[5,12,28,74,89,94,101],"improving":[6],"on":[7,17],"a":[8,76],"transistor":[9],"sizing":[10],"method":[11,36],"CMOS":[13],"gates,":[14,41],"which":[15],"relies":[16],"upsizing":[18],"the":[19,24,30,45,51],"length":[20],"(L)":[21],"and":[22,58,91,104,127],"balancing":[23],"voltage":[25,47,53],"transfer":[26],"characteristics":[27],"maximizing":[29],"static":[31],"noise":[32],"margins":[33],"(SNM's).":[34],"The":[35],"leads":[37],"to":[38,83,97,129],"highly":[39],"reliable":[40],"operating":[42],"correctly":[43],"over":[44],"whole":[46],"range.":[48],"Besides":[49],"calculating":[50],"threshold":[52],"(Vth)":[54],"exactly":[55],"(precise":[56],"L's)":[57],"having":[59,75,84],"more":[60],"accurate":[61],"SNMs":[62],"(maximum":[63],"square":[64],"method),":[65],"in":[66],"this":[67],"we":[69],"shall":[70],"use":[71],"biasing":[72],"(Vbs)":[73],"single":[77],"Loptfor":[78],"all":[79],"transistors":[80],"(as":[81],"opposed":[82],"two":[85],"different":[86],"Lopt,":[87],"one":[88,93],"nMOS":[90],"another":[92],"pMOS)":[95],"leading":[96],"better":[98],"manufacturability.":[99],"Simulations":[100],"INV,":[102],"NAND-2,":[103],"NOR-2":[105],"show":[106],"that":[107],"although":[108],"Vthand":[109],"L":[110],"change":[111],"by":[112,114],"~10%,":[113],"using":[115],"Vbswe":[116],"can":[117],"still":[118],"achieve":[119],"very":[120],"high":[121],"SNM's,":[122],"while":[123],"additionally":[124],"reducing":[125],"power":[126],"energy":[128],"~50%.":[130]},"counts_by_year":[{"year":2014,"cited_by_count":2}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}