{"id":"https://openalex.org/W1993916273","doi":"https://doi.org/10.1109/icecs.2013.6815379","title":"High throughput hardware design for the HEVC Fractional Motion Estimation Interpolation Unit","display_name":"High throughput hardware design for the HEVC Fractional Motion Estimation Interpolation Unit","publication_year":2013,"publication_date":"2013-12-01","ids":{"openalex":"https://openalex.org/W1993916273","doi":"https://doi.org/10.1109/icecs.2013.6815379","mag":"1993916273"},"language":"en","primary_location":{"id":"doi:10.1109/icecs.2013.6815379","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecs.2013.6815379","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5053360445","display_name":"Henrique Maich","orcid":null},"institutions":[{"id":"https://openalex.org/I169248161","display_name":"Universidade Federal de Pelotas","ror":"https://ror.org/05msy9z54","country_code":"BR","type":"education","lineage":["https://openalex.org/I169248161"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Henrique Maich","raw_affiliation_strings":["Group of Architectures and Integrated Circuits, UFPel, Pelotas, Brazil","Federal University of Pelotas, Group of Architectures and Integrated Circuits - UFPel - Pelotas, Brazil"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Group of Architectures and Integrated Circuits, UFPel, Pelotas, Brazil","institution_ids":["https://openalex.org/I169248161"]},{"raw_affiliation_string":"Federal University of Pelotas, Group of Architectures and Integrated Circuits - UFPel - Pelotas, Brazil","institution_ids":["https://openalex.org/I169248161"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5034889625","display_name":"Vladimir Afonso","orcid":"https://orcid.org/0000-0002-5761-4121"},"institutions":[{"id":"https://openalex.org/I169248161","display_name":"Universidade Federal de Pelotas","ror":"https://ror.org/05msy9z54","country_code":"BR","type":"education","lineage":["https://openalex.org/I169248161"]},{"id":"https://openalex.org/I4210155777","display_name":"Instituto Federal Sul-rio-grandense","ror":"https://ror.org/05dr32318","country_code":"BR","type":"education","lineage":["https://openalex.org/I4210155777"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Vladimir Afonso","raw_affiliation_strings":["Sul-rio-grandense Federal Institute, IFSul, Pelotas, Brazil","Federal University of Pelotas, Group of Architectures and Integrated Circuits - UFPel - Pelotas, Brazil"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Sul-rio-grandense Federal Institute, IFSul, Pelotas, Brazil","institution_ids":["https://openalex.org/I4210155777"]},{"raw_affiliation_string":"Federal University of Pelotas, Group of Architectures and Integrated Circuits - UFPel - Pelotas, Brazil","institution_ids":["https://openalex.org/I169248161"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5013542218","display_name":"Denis Teixeira Franco","orcid":null},"institutions":[{"id":"https://openalex.org/I169248161","display_name":"Universidade Federal de Pelotas","ror":"https://ror.org/05msy9z54","country_code":"BR","type":"education","lineage":["https://openalex.org/I169248161"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Denis Franco","raw_affiliation_strings":["Group of Architectures and Integrated Circuits, UFPel, Pelotas, Brazil","Federal University of Pelotas, Group of Architectures and Integrated Circuits - UFPel - Pelotas, Brazil"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Group of Architectures and Integrated Circuits, UFPel, Pelotas, Brazil","institution_ids":["https://openalex.org/I169248161"]},{"raw_affiliation_string":"Federal University of Pelotas, Group of Architectures and Integrated Circuits - UFPel - Pelotas, Brazil","institution_ids":["https://openalex.org/I169248161"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5057414253","display_name":"Bruno Zatt","orcid":"https://orcid.org/0000-0002-8045-957X"},"institutions":[{"id":"https://openalex.org/I169248161","display_name":"Universidade Federal de Pelotas","ror":"https://ror.org/05msy9z54","country_code":"BR","type":"education","lineage":["https://openalex.org/I169248161"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Bruno Zatt","raw_affiliation_strings":["Group of Architectures and Integrated Circuits, UFPel, Pelotas, Brazil","Federal University of Pelotas, Group of Architectures and Integrated Circuits - UFPel - Pelotas, Brazil"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Group of Architectures and Integrated Circuits, UFPel, Pelotas, Brazil","institution_ids":["https://openalex.org/I169248161"]},{"raw_affiliation_string":"Federal University of Pelotas, Group of Architectures and Integrated Circuits - UFPel - Pelotas, Brazil","institution_ids":["https://openalex.org/I169248161"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5081630912","display_name":"Marcelo Porto","orcid":"https://orcid.org/0000-0003-3827-3023"},"institutions":[{"id":"https://openalex.org/I169248161","display_name":"Universidade Federal de Pelotas","ror":"https://ror.org/05msy9z54","country_code":"BR","type":"education","lineage":["https://openalex.org/I169248161"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Marcelo Porto","raw_affiliation_strings":["Group of Architectures and Integrated Circuits, UFPel, Pelotas, Brazil","Federal University of Pelotas, Group of Architectures and Integrated Circuits - UFPel - Pelotas, Brazil"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Group of Architectures and Integrated Circuits, UFPel, Pelotas, Brazil","institution_ids":["https://openalex.org/I169248161"]},{"raw_affiliation_string":"Federal University of Pelotas, Group of Architectures and Integrated Circuits - UFPel - Pelotas, Brazil","institution_ids":["https://openalex.org/I169248161"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5070735330","display_name":"Luciano Agostini","orcid":"https://orcid.org/0000-0002-3421-5830"},"institutions":[{"id":"https://openalex.org/I169248161","display_name":"Universidade Federal de Pelotas","ror":"https://ror.org/05msy9z54","country_code":"BR","type":"education","lineage":["https://openalex.org/I169248161"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Luciano Agostini","raw_affiliation_strings":["Group of Architectures and Integrated Circuits, UFPel, Pelotas, Brazil","Federal University of Pelotas, Group of Architectures and Integrated Circuits - UFPel - Pelotas, Brazil"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Group of Architectures and Integrated Circuits, UFPel, Pelotas, Brazil","institution_ids":["https://openalex.org/I169248161"]},{"raw_affiliation_string":"Federal University of Pelotas, Group of Architectures and Integrated Circuits - UFPel - Pelotas, Brazil","institution_ids":["https://openalex.org/I169248161"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":6,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.6442,"has_fulltext":false,"cited_by_count":10,"citation_normalized_percentile":{"value":0.67113164,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"161","last_page":"164"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10741","display_name":"Video Coding and Compression Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10741","display_name":"Video Coding and Compression Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10531","display_name":"Advanced Vision and Imaging","score":0.9983999729156494,"subfield":{"id":"https://openalex.org/subfields/1707","display_name":"Computer Vision and Pattern Recognition"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10901","display_name":"Advanced Data Compression Techniques","score":0.9965000152587891,"subfield":{"id":"https://openalex.org/subfields/1707","display_name":"Computer Vision and Pattern Recognition"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/stratix","display_name":"Stratix","score":0.8366597890853882},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7771583199501038},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6951197981834412},{"id":"https://openalex.org/keywords/hardware-architecture","display_name":"Hardware architecture","score":0.6175472736358643},{"id":"https://openalex.org/keywords/motion-estimation","display_name":"Motion estimation","score":0.6148455142974854},{"id":"https://openalex.org/keywords/coding","display_name":"Coding (social sciences)","score":0.5865804553031921},{"id":"https://openalex.org/keywords/reference-software","display_name":"Reference software","score":0.48755496740341187},{"id":"https://openalex.org/keywords/throughput","display_name":"Throughput","score":0.48133715987205505},{"id":"https://openalex.org/keywords/vhdl","display_name":"VHDL","score":0.47805503010749817},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.45924192667007446},{"id":"https://openalex.org/keywords/interpolation","display_name":"Interpolation (computer graphics)","score":0.45736226439476013},{"id":"https://openalex.org/keywords/hardware-description-language","display_name":"Hardware description language","score":0.4509831666946411},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.402046799659729},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.398732453584671},{"id":"https://openalex.org/keywords/real-time-computing","display_name":"Real-time computing","score":0.37670576572418213},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.19400951266288757},{"id":"https://openalex.org/keywords/motion","display_name":"Motion (physics)","score":0.1258079707622528},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.1244688332080841},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.07633191347122192},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.07225000858306885}],"concepts":[{"id":"https://openalex.org/C2776277307","wikidata":"https://www.wikidata.org/wiki/Q22074755","display_name":"Stratix","level":3,"score":0.8366597890853882},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7771583199501038},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6951197981834412},{"id":"https://openalex.org/C65232700","wikidata":"https://www.wikidata.org/wiki/Q5656403","display_name":"Hardware architecture","level":3,"score":0.6175472736358643},{"id":"https://openalex.org/C10161872","wikidata":"https://www.wikidata.org/wiki/Q557891","display_name":"Motion estimation","level":2,"score":0.6148455142974854},{"id":"https://openalex.org/C179518139","wikidata":"https://www.wikidata.org/wiki/Q5140297","display_name":"Coding (social sciences)","level":2,"score":0.5865804553031921},{"id":"https://openalex.org/C2776493296","wikidata":"https://www.wikidata.org/wiki/Q7307150","display_name":"Reference software","level":3,"score":0.48755496740341187},{"id":"https://openalex.org/C157764524","wikidata":"https://www.wikidata.org/wiki/Q1383412","display_name":"Throughput","level":3,"score":0.48133715987205505},{"id":"https://openalex.org/C36941000","wikidata":"https://www.wikidata.org/wiki/Q209455","display_name":"VHDL","level":3,"score":0.47805503010749817},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.45924192667007446},{"id":"https://openalex.org/C137800194","wikidata":"https://www.wikidata.org/wiki/Q11713455","display_name":"Interpolation (computer graphics)","level":3,"score":0.45736226439476013},{"id":"https://openalex.org/C42143788","wikidata":"https://www.wikidata.org/wiki/Q173341","display_name":"Hardware description language","level":3,"score":0.4509831666946411},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.402046799659729},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.398732453584671},{"id":"https://openalex.org/C79403827","wikidata":"https://www.wikidata.org/wiki/Q3988","display_name":"Real-time computing","level":1,"score":0.37670576572418213},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.19400951266288757},{"id":"https://openalex.org/C104114177","wikidata":"https://www.wikidata.org/wiki/Q79782","display_name":"Motion (physics)","level":2,"score":0.1258079707622528},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.1244688332080841},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.07633191347122192},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.07225000858306885},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0},{"id":"https://openalex.org/C555944384","wikidata":"https://www.wikidata.org/wiki/Q249","display_name":"Wireless","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/icecs.2013.6815379","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecs.2013.6815379","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.5799999833106995,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W2041390571","https://openalex.org/W2119788764","https://openalex.org/W2132363810","https://openalex.org/W2145115307","https://openalex.org/W2146029364","https://openalex.org/W2146395539","https://openalex.org/W3145280868"],"related_works":["https://openalex.org/W2110818533","https://openalex.org/W1917852300","https://openalex.org/W2384838054","https://openalex.org/W2139058049","https://openalex.org/W2548456620","https://openalex.org/W2376018793","https://openalex.org/W2911649771","https://openalex.org/W2169179842","https://openalex.org/W2148697719","https://openalex.org/W1993916273"],"abstract_inverted_index":{"This":[0,44],"paper":[1],"presents":[2],"a":[3,108],"hardware":[4],"design":[5],"for":[6],"the":[7,16,41,54,61,93],"Fractional":[8],"Motion":[9],"Estimation":[10],"(FME)":[11],"Interpolation":[12],"Unit":[13,33],"compatible":[14],"with":[15,107],"High":[17],"Efficiency":[18],"Video":[19],"Coding":[20],"(HEVC)":[21],"standard.":[22],"The":[23,74,89],"proposed":[24],"architecture":[25,76,95],"was":[26,46,77],"designed":[27,75,94],"to":[28,38,58,83,98],"consider":[29],"fixed":[30],"16\u00d716":[31],"Prediction":[32],"(PU)":[34],"size":[35,68],"in":[36,79],"order":[37],"drastically":[39],"reduce":[40],"computational":[42],"effort.":[43],"decision":[45],"made":[47],"taking":[48],"into":[49],"account":[50],"several":[51],"evaluations,":[52],"using":[53],"HEVC":[55],"Reference":[56],"Software,":[57],"find":[59],"out":[60],"number":[62],"of":[63,65],"occurrences":[64],"each":[66],"PU":[67],"and":[69,81],"their":[70],"coding":[71],"efficiency":[72],"impact.":[73],"described":[78],"VHDL":[80],"synthesized":[82],"an":[84],"Altera":[85],"Stratix":[86],"III":[87],"FPGA.":[88],"results":[90],"show":[91],"that":[92],"is":[96],"able":[97],"process":[99],"QFHD":[100],"videos":[101],"at":[102],"60":[103],"frames":[104],"per":[105],"second":[106],"353.8":[109],"MHz":[110],"clock":[111],"frequency.":[112]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2020,"cited_by_count":3},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":2},{"year":2017,"cited_by_count":1},{"year":2015,"cited_by_count":2}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}