{"id":"https://openalex.org/W1999486972","doi":"https://doi.org/10.1109/icecs.2013.6815339","title":"Low-power design of hybrid digital impedance calibration for process, voltage, temperature compensations","display_name":"Low-power design of hybrid digital impedance calibration for process, voltage, temperature compensations","publication_year":2013,"publication_date":"2013-12-01","ids":{"openalex":"https://openalex.org/W1999486972","doi":"https://doi.org/10.1109/icecs.2013.6815339","mag":"1999486972"},"language":"en","primary_location":{"id":"doi:10.1109/icecs.2013.6815339","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecs.2013.6815339","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5057245386","display_name":"Yuan Fang","orcid":"https://orcid.org/0000-0003-1918-0817"},"institutions":[{"id":"https://openalex.org/I31512782","display_name":"Technische Universit\u00e4t Darmstadt","ror":"https://ror.org/05n911h24","country_code":"DE","type":"education","lineage":["https://openalex.org/I31512782"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Yuan Fang","raw_affiliation_strings":["Integrated Electronic Systems Lab, Technische Universitaet Darmstadt, Darmstadt, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Integrated Electronic Systems Lab, Technische Universitaet Darmstadt, Darmstadt, Germany","institution_ids":["https://openalex.org/I31512782"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5066493223","display_name":"Uzair Muhammad","orcid":null},"institutions":[{"id":"https://openalex.org/I31512782","display_name":"Technische Universit\u00e4t Darmstadt","ror":"https://ror.org/05n911h24","country_code":"DE","type":"education","lineage":["https://openalex.org/I31512782"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Uzair Muhammad","raw_affiliation_strings":["Integrated Electronic Systems Lab, Technische Universitaet Darmstadt, Darmstadt, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Integrated Electronic Systems Lab, Technische Universitaet Darmstadt, Darmstadt, Germany","institution_ids":["https://openalex.org/I31512782"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5084365514","display_name":"A K Jaiswal","orcid":"https://orcid.org/0000-0003-3724-0027"},"institutions":[{"id":"https://openalex.org/I31512782","display_name":"Technische Universit\u00e4t Darmstadt","ror":"https://ror.org/05n911h24","country_code":"DE","type":"education","lineage":["https://openalex.org/I31512782"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Ashok Jaiswal","raw_affiliation_strings":["Integrated Electronic Systems Lab, Technische Universitaet Darmstadt, Darmstadt, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Integrated Electronic Systems Lab, Technische Universitaet Darmstadt, Darmstadt, Germany","institution_ids":["https://openalex.org/I31512782"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5061804977","display_name":"Klaus Hofmann","orcid":"https://orcid.org/0000-0002-6675-0221"},"institutions":[{"id":"https://openalex.org/I31512782","display_name":"Technische Universit\u00e4t Darmstadt","ror":"https://ror.org/05n911h24","country_code":"DE","type":"education","lineage":["https://openalex.org/I31512782"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Klaus Hofmann","raw_affiliation_strings":["Integrated Electronic Systems Lab, Technische Universitaet Darmstadt, Darmstadt, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Integrated Electronic Systems Lab, Technische Universitaet Darmstadt, Darmstadt, Germany","institution_ids":["https://openalex.org/I31512782"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.0774961,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"37","last_page":"40"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/impedance-matching","display_name":"Impedance matching","score":0.7176347374916077},{"id":"https://openalex.org/keywords/calibration","display_name":"Calibration","score":0.6973044276237488},{"id":"https://openalex.org/keywords/electrical-impedance","display_name":"Electrical impedance","score":0.6215556859970093},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5960513353347778},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.5526061654090881},{"id":"https://openalex.org/keywords/signal","display_name":"SIGNAL (programming language)","score":0.5318999290466309},{"id":"https://openalex.org/keywords/output-impedance","display_name":"Output impedance","score":0.5167195200920105},{"id":"https://openalex.org/keywords/signal-integrity","display_name":"Signal integrity","score":0.5127707123756409},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.4955936670303345},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.41128936409950256},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.3716491758823395},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.3269474506378174},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.09120979905128479}],"concepts":[{"id":"https://openalex.org/C612350","wikidata":"https://www.wikidata.org/wiki/Q1761108","display_name":"Impedance matching","level":3,"score":0.7176347374916077},{"id":"https://openalex.org/C165838908","wikidata":"https://www.wikidata.org/wiki/Q736777","display_name":"Calibration","level":2,"score":0.6973044276237488},{"id":"https://openalex.org/C17829176","wikidata":"https://www.wikidata.org/wiki/Q179043","display_name":"Electrical impedance","level":2,"score":0.6215556859970093},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5960513353347778},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.5526061654090881},{"id":"https://openalex.org/C2779843651","wikidata":"https://www.wikidata.org/wiki/Q7390335","display_name":"SIGNAL (programming language)","level":2,"score":0.5318999290466309},{"id":"https://openalex.org/C58112919","wikidata":"https://www.wikidata.org/wiki/Q631203","display_name":"Output impedance","level":3,"score":0.5167195200920105},{"id":"https://openalex.org/C44938667","wikidata":"https://www.wikidata.org/wiki/Q4503810","display_name":"Signal integrity","level":3,"score":0.5127707123756409},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.4955936670303345},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.41128936409950256},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.3716491758823395},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.3269474506378174},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.09120979905128479},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C120793396","wikidata":"https://www.wikidata.org/wiki/Q173350","display_name":"Printed circuit board","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/icecs.2013.6815339","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecs.2013.6815339","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.8500000238418579,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W1562126234","https://openalex.org/W2079469916","https://openalex.org/W2123134748","https://openalex.org/W2131629103","https://openalex.org/W2159415810","https://openalex.org/W2216127957","https://openalex.org/W2405329158"],"related_works":["https://openalex.org/W2539286897","https://openalex.org/W2087608731","https://openalex.org/W2357985750","https://openalex.org/W2145437567","https://openalex.org/W1486956228","https://openalex.org/W4297786912","https://openalex.org/W2126751867","https://openalex.org/W2358535266","https://openalex.org/W2136855998","https://openalex.org/W2020934979"],"abstract_inverted_index":{"In":[0,56],"advanced":[1],"high-speed":[2,41],"communication":[3],"systems,":[4],"I/O":[5,44],"interfaces":[6],"require":[7],"precise":[8],"impedance":[9,33,97],"matching":[10],"to":[11,20,58,86],"maintain":[12],"signal":[13,17],"integrity":[14],"and":[15,77,100],"avoid":[16],"reflections":[18],"due":[19],"process,":[21],"voltage,":[22],"temperature":[23],"(PVT)":[24],"variations.":[25],"This":[26],"paper":[27],"presents":[28],"a":[29,48],"power-efficient":[30],"hybrid":[31,66],"digital":[32],"calibration":[34,38,71],"technique":[35],"with":[36],"short":[37],"time.":[39],"A":[40],"GDDR5":[42],"memory":[43],"is":[45],"taken":[46],"as":[47],"case":[49],"study":[50],"in":[51],"TSMC":[52],"65nm":[53],"LP":[54],"technology.":[55],"comparison":[57],"the":[59,64,70,83],"conventional":[60],"binary":[61],"search":[62],"algorithm":[63,67],"proposed":[65],"can":[68],"reduce":[69],"time":[72],"by":[73,79],"more":[74],"than":[75],"12%":[76],"power":[78],"8.91":[80],"mW":[81],"for":[82,98,102],"corners":[84],"close":[85],"reference":[87],"Vdd/2.":[88],"The":[89],"impedances":[90],"are":[91],"calibrated":[92],"within":[93],"+/-2%":[94],"of":[95],"target":[96],"PFET":[99],"+3.3%/-2.8%":[101],"NFET.":[103]},"counts_by_year":[],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}