{"id":"https://openalex.org/W2024834688","doi":"https://doi.org/10.1109/icecs.2012.6463548","title":"Dedicated FPGA communication architecture and design for a large-scale neuromorphic system","display_name":"Dedicated FPGA communication architecture and design for a large-scale neuromorphic system","publication_year":2012,"publication_date":"2012-12-01","ids":{"openalex":"https://openalex.org/W2024834688","doi":"https://doi.org/10.1109/icecs.2012.6463548","mag":"2024834688"},"language":"en","primary_location":{"id":"doi:10.1109/icecs.2012.6463548","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecs.2012.6463548","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5016521237","display_name":"Vasilis Thanasoulis","orcid":null},"institutions":[{"id":"https://openalex.org/I78650965","display_name":"TU Dresden","ror":"https://ror.org/042aqky30","country_code":"DE","type":"education","lineage":["https://openalex.org/I78650965"]}],"countries":["DE"],"is_corresponding":true,"raw_author_name":"V. Thanasoulis","raw_affiliation_strings":["Endowed Chair for Parallel VLSI Systems and Neuromorphic Circuits, Technische Universit\u00e4t Dresden, Germany","Parallel VLSI Syst. & Neuromorphic Circuits, Tech. Univ. Dresden, Dresden, Germany"],"affiliations":[{"raw_affiliation_string":"Endowed Chair for Parallel VLSI Systems and Neuromorphic Circuits, Technische Universit\u00e4t Dresden, Germany","institution_ids":["https://openalex.org/I78650965"]},{"raw_affiliation_string":"Parallel VLSI Syst. & Neuromorphic Circuits, Tech. Univ. Dresden, Dresden, Germany","institution_ids":["https://openalex.org/I78650965"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5003942211","display_name":"Johannes Partzsch","orcid":"https://orcid.org/0000-0002-6286-5064"},"institutions":[{"id":"https://openalex.org/I78650965","display_name":"TU Dresden","ror":"https://ror.org/042aqky30","country_code":"DE","type":"education","lineage":["https://openalex.org/I78650965"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"J. Partzsch","raw_affiliation_strings":["Endowed Chair for Parallel VLSI Systems and Neuromorphic Circuits, Technische Universit\u00e4t Dresden, Germany","Parallel VLSI Syst. & Neuromorphic Circuits, Tech. Univ. Dresden, Dresden, Germany"],"affiliations":[{"raw_affiliation_string":"Endowed Chair for Parallel VLSI Systems and Neuromorphic Circuits, Technische Universit\u00e4t Dresden, Germany","institution_ids":["https://openalex.org/I78650965"]},{"raw_affiliation_string":"Parallel VLSI Syst. & Neuromorphic Circuits, Tech. Univ. Dresden, Dresden, Germany","institution_ids":["https://openalex.org/I78650965"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5052216639","display_name":"Stephan Hartmann","orcid":null},"institutions":[{"id":"https://openalex.org/I78650965","display_name":"TU Dresden","ror":"https://ror.org/042aqky30","country_code":"DE","type":"education","lineage":["https://openalex.org/I78650965"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"S. Hartmann","raw_affiliation_strings":["Endowed Chair for Parallel VLSI Systems and Neuromorphic Circuits, Technische Universit\u00e4t Dresden, Germany","Parallel VLSI Syst. & Neuromorphic Circuits, Tech. Univ. Dresden, Dresden, Germany"],"affiliations":[{"raw_affiliation_string":"Endowed Chair for Parallel VLSI Systems and Neuromorphic Circuits, Technische Universit\u00e4t Dresden, Germany","institution_ids":["https://openalex.org/I78650965"]},{"raw_affiliation_string":"Parallel VLSI Syst. & Neuromorphic Circuits, Tech. Univ. Dresden, Dresden, Germany","institution_ids":["https://openalex.org/I78650965"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5071241846","display_name":"Christian Mayr","orcid":"https://orcid.org/0000-0003-3502-0872"},"institutions":[{"id":"https://openalex.org/I78650965","display_name":"TU Dresden","ror":"https://ror.org/042aqky30","country_code":"DE","type":"education","lineage":["https://openalex.org/I78650965"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"C. Mayr","raw_affiliation_strings":["Endowed Chair for Parallel VLSI Systems and Neuromorphic Circuits, Technische Universit\u00e4t Dresden, Germany","Parallel VLSI Syst. & Neuromorphic Circuits, Tech. Univ. Dresden, Dresden, Germany"],"affiliations":[{"raw_affiliation_string":"Endowed Chair for Parallel VLSI Systems and Neuromorphic Circuits, Technische Universit\u00e4t Dresden, Germany","institution_ids":["https://openalex.org/I78650965"]},{"raw_affiliation_string":"Parallel VLSI Syst. & Neuromorphic Circuits, Tech. Univ. Dresden, Dresden, Germany","institution_ids":["https://openalex.org/I78650965"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5110046407","display_name":"Ren\u00e9 Sch\u00fcffny","orcid":null},"institutions":[{"id":"https://openalex.org/I78650965","display_name":"TU Dresden","ror":"https://ror.org/042aqky30","country_code":"DE","type":"education","lineage":["https://openalex.org/I78650965"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"R. Schuffny","raw_affiliation_strings":["Endowed Chair for Parallel VLSI Systems and Neuromorphic Circuits, Technische Universit\u00e4t Dresden, Germany","Parallel VLSI Syst. & Neuromorphic Circuits, Tech. Univ. Dresden, Dresden, Germany"],"affiliations":[{"raw_affiliation_string":"Endowed Chair for Parallel VLSI Systems and Neuromorphic Circuits, Technische Universit\u00e4t Dresden, Germany","institution_ids":["https://openalex.org/I78650965"]},{"raw_affiliation_string":"Parallel VLSI Syst. & Neuromorphic Circuits, Tech. Univ. Dresden, Dresden, Germany","institution_ids":["https://openalex.org/I78650965"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5016521237"],"corresponding_institution_ids":["https://openalex.org/I78650965"],"apc_list":null,"apc_paid":null,"fwci":0.7365,"has_fulltext":false,"cited_by_count":10,"citation_normalized_percentile":{"value":0.73728323,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":"23","issue":null,"first_page":"877","last_page":"880"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11601","display_name":"Neuroscience and Neural Engineering","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2804","display_name":"Cellular and Molecular Neuroscience"},"field":{"id":"https://openalex.org/fields/28","display_name":"Neuroscience"},"domain":{"id":"https://openalex.org/domains/1","display_name":"Life Sciences"}},{"id":"https://openalex.org/T11992","display_name":"CCD and CMOS Imaging Sensors","score":0.9986000061035156,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/neuromorphic-engineering","display_name":"Neuromorphic engineering","score":0.928908109664917},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7520667910575867},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6334837675094604},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5605279803276062},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.5087178349494934},{"id":"https://openalex.org/keywords/node","display_name":"Node (physics)","score":0.5050328373908997},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.47644904255867004},{"id":"https://openalex.org/keywords/throughput","display_name":"Throughput","score":0.4535854160785675},{"id":"https://openalex.org/keywords/network-packet","display_name":"Network packet","score":0.4357908368110657},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3942282795906067},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.21477103233337402},{"id":"https://openalex.org/keywords/artificial-neural-network","display_name":"Artificial neural network","score":0.16146337985992432},{"id":"https://openalex.org/keywords/wireless","display_name":"Wireless","score":0.14549043774604797},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.12264084815979004},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.10088276863098145}],"concepts":[{"id":"https://openalex.org/C151927369","wikidata":"https://www.wikidata.org/wiki/Q1981312","display_name":"Neuromorphic engineering","level":3,"score":0.928908109664917},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7520667910575867},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6334837675094604},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5605279803276062},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.5087178349494934},{"id":"https://openalex.org/C62611344","wikidata":"https://www.wikidata.org/wiki/Q1062658","display_name":"Node (physics)","level":2,"score":0.5050328373908997},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.47644904255867004},{"id":"https://openalex.org/C157764524","wikidata":"https://www.wikidata.org/wiki/Q1383412","display_name":"Throughput","level":3,"score":0.4535854160785675},{"id":"https://openalex.org/C158379750","wikidata":"https://www.wikidata.org/wiki/Q214111","display_name":"Network packet","level":2,"score":0.4357908368110657},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3942282795906067},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.21477103233337402},{"id":"https://openalex.org/C50644808","wikidata":"https://www.wikidata.org/wiki/Q192776","display_name":"Artificial neural network","level":2,"score":0.16146337985992432},{"id":"https://openalex.org/C555944384","wikidata":"https://www.wikidata.org/wiki/Q249","display_name":"Wireless","level":2,"score":0.14549043774604797},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.12264084815979004},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.10088276863098145},{"id":"https://openalex.org/C119857082","wikidata":"https://www.wikidata.org/wiki/Q2539","display_name":"Machine learning","level":1,"score":0.0},{"id":"https://openalex.org/C66938386","wikidata":"https://www.wikidata.org/wiki/Q633538","display_name":"Structural engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/icecs.2012.6463548","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecs.2012.6463548","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.6200000047683716,"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":16,"referenced_works":["https://openalex.org/W1590810061","https://openalex.org/W1674145689","https://openalex.org/W1996446221","https://openalex.org/W2060151352","https://openalex.org/W2069552454","https://openalex.org/W2073094401","https://openalex.org/W2095725009","https://openalex.org/W2111087492","https://openalex.org/W2122872855","https://openalex.org/W2124759970","https://openalex.org/W2128949090","https://openalex.org/W2156903694","https://openalex.org/W2402844613","https://openalex.org/W4236546623","https://openalex.org/W6678541873","https://openalex.org/W6713295671"],"related_works":["https://openalex.org/W2986579802","https://openalex.org/W3108691306","https://openalex.org/W4389237622","https://openalex.org/W2166309310","https://openalex.org/W4385753159","https://openalex.org/W4200152843","https://openalex.org/W4214914769","https://openalex.org/W4387251107","https://openalex.org/W4317717548","https://openalex.org/W4297621941"],"abstract_inverted_index":{"The":[0,67],"communication":[1,41],"infrastructure":[2],"is":[3,14,106],"a":[4,39,64,70,78,87],"crucial":[5],"part":[6],"of":[7,19,34,59,98],"neuromorphic":[8,61,112],"VLSI":[9],"systems.":[10],"A":[11],"sophisticated":[12],"network":[13,42],"required":[15],"for":[16,31,73,115],"the":[17,23,28,32,35,54,60,99],"transmission":[18],"pulse":[20,48,93],"events":[21],"among":[22],"individual":[24],"neuron-and-synapse":[25],"circuits":[26],"and":[27,52,57,76,80,96,120],"configuration":[29,58],"data":[30,82],"components":[33],"system.":[36],"We":[37],"present":[38],"packet-based":[40],"implemented":[43],"on":[44],"FPGA":[45],"that":[46,91],"provides":[47],"stimulation,":[49],"inter-node":[50],"connectivity":[51],"allows":[53],"complete":[55],"control":[56],"system":[62,117],"by":[63],"host":[65],"unit.":[66],"design":[68],"deploys":[69],"specific":[71],"architecture":[72],"optimized":[74],"throughput":[75],"implements":[77],"reliable":[79],"ordered":[81],"delivery.":[83],"It":[84],"employs":[85],"also":[86],"large":[88],"Playback/Trace":[89],"memory":[90],"offers":[92],"event":[94],"replay":[95],"recording":[97],"produced":[100],"neuronal":[101],"activity.":[102],"Altogether,":[103],"our":[104],"implementation":[105],"more":[107],"versatile":[108],"than":[109],"recent":[110],"FPGA-based":[111],"infrastructures,":[113],"allowing":[114],"fast":[116],"configuration,":[118],"stimulation":[119],"monitoring.":[121]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":2},{"year":2021,"cited_by_count":2},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2014,"cited_by_count":2},{"year":2012,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}