{"id":"https://openalex.org/W2024224226","doi":"https://doi.org/10.1109/icecs.2011.6122333","title":"Efficient periodic clock calculus in latency-insensitive design","display_name":"Efficient periodic clock calculus in latency-insensitive design","publication_year":2011,"publication_date":"2011-12-01","ids":{"openalex":"https://openalex.org/W2024224226","doi":"https://doi.org/10.1109/icecs.2011.6122333","mag":"2024224226"},"language":"en","primary_location":{"id":"doi:10.1109/icecs.2011.6122333","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecs.2011.6122333","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5021711769","display_name":"Mahdi Zare","orcid":"https://orcid.org/0000-0003-1151-9767"},"institutions":[{"id":"https://openalex.org/I4210116438","display_name":"Islamic Azad University, Shahr-e-Qods Branch","ror":"https://ror.org/022ca9x91","country_code":"IR","type":"education","lineage":["https://openalex.org/I110525433","https://openalex.org/I4210116438"]},{"id":"https://openalex.org/I110525433","display_name":"Islamic Azad University, Tehran","ror":"https://ror.org/01kzn7k21","country_code":"IR","type":"education","lineage":["https://openalex.org/I110525433"]}],"countries":["IR"],"is_corresponding":true,"raw_author_name":"Mahdi Zare","raw_affiliation_strings":["Department of Electronic Engineering, Islamic Azad University, Tehran, Iran","Department of Electronic Engineering, Shahr-e-Qods Branch, Islamic Azad University, Tehran, Iran"],"affiliations":[{"raw_affiliation_string":"Department of Electronic Engineering, Islamic Azad University, Tehran, Iran","institution_ids":["https://openalex.org/I110525433"]},{"raw_affiliation_string":"Department of Electronic Engineering, Shahr-e-Qods Branch, Islamic Azad University, Tehran, Iran","institution_ids":["https://openalex.org/I4210116438"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5091774451","display_name":"Shaahin Hessabi","orcid":"https://orcid.org/0000-0003-3193-2567"},"institutions":[{"id":"https://openalex.org/I133529467","display_name":"Sharif University of Technology","ror":"https://ror.org/024c2fq17","country_code":"IR","type":"education","lineage":["https://openalex.org/I133529467"]}],"countries":["IR"],"is_corresponding":false,"raw_author_name":"Shaahin Hessabi","raw_affiliation_strings":["Department of Computer Engineering, Sharif University of Technology, Tehran, Iran"],"affiliations":[{"raw_affiliation_string":"Department of Computer Engineering, Sharif University of Technology, Tehran, Iran","institution_ids":["https://openalex.org/I133529467"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5045308844","display_name":"Maziar Goudarzi","orcid":"https://orcid.org/0000-0002-1272-4589"},"institutions":[{"id":"https://openalex.org/I133529467","display_name":"Sharif University of Technology","ror":"https://ror.org/024c2fq17","country_code":"IR","type":"education","lineage":["https://openalex.org/I133529467"]}],"countries":["IR"],"is_corresponding":false,"raw_author_name":"Maziar Goudarzi","raw_affiliation_strings":["Department of Computer Engineering, Sharif University of Technology, Tehran, Iran"],"affiliations":[{"raw_affiliation_string":"Department of Computer Engineering, Sharif University of Technology, Tehran, Iran","institution_ids":["https://openalex.org/I133529467"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5021711769"],"corresponding_institution_ids":["https://openalex.org/I4210116438","https://openalex.org/I110525433"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.0880521,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"546","last_page":"549"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7299643754959106},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.6059210896492004},{"id":"https://openalex.org/keywords/scheduling","display_name":"Scheduling (production processes)","score":0.5770757794380188},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.47487208247184753},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.45394399762153625},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.18538817763328552},{"id":"https://openalex.org/keywords/mathematical-optimization","display_name":"Mathematical optimization","score":0.17219114303588867}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7299643754959106},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.6059210896492004},{"id":"https://openalex.org/C206729178","wikidata":"https://www.wikidata.org/wiki/Q2271896","display_name":"Scheduling (production processes)","level":2,"score":0.5770757794380188},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.47487208247184753},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.45394399762153625},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.18538817763328552},{"id":"https://openalex.org/C126255220","wikidata":"https://www.wikidata.org/wiki/Q141495","display_name":"Mathematical optimization","level":1,"score":0.17219114303588867},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/icecs.2011.6122333","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecs.2011.6122333","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":9,"referenced_works":["https://openalex.org/W1985129697","https://openalex.org/W1991466857","https://openalex.org/W2021433439","https://openalex.org/W2099034654","https://openalex.org/W2100720925","https://openalex.org/W2144148413","https://openalex.org/W2147013386","https://openalex.org/W4240110784","https://openalex.org/W6681131238"],"related_works":["https://openalex.org/W2748952813","https://openalex.org/W2051487156","https://openalex.org/W2073681303","https://openalex.org/W2390279801","https://openalex.org/W2358668433","https://openalex.org/W2376932109","https://openalex.org/W2001405890","https://openalex.org/W2382290278","https://openalex.org/W2350741829","https://openalex.org/W2530322880"],"abstract_inverted_index":{"Communication":[0],"wire":[1,26],"delay":[2],"between":[3],"multiple":[4],"blocks":[5],"is":[6,21],"becoming":[7],"a":[8,22,30],"critical":[9],"issue":[10],"in":[11,45,89,111],"System":[12],"on":[13,104],"Chip":[14],"(SoC)":[15],"design.":[16],"Scheduling-based":[17],"Latency-Insensitive":[18],"Design":[19],"(LID)":[20],"method":[23],"to":[24,108],"alleviate":[25],"delays":[27],"by":[28],"utilizing":[29],"central":[31],"scheduling":[32,42,75],"scheme":[33,43],"for":[34],"periodic":[35],"clock":[36],"gating":[37],"of":[38,50,73,113],"the":[39,71,74,92,99],"blocks.":[40],"The":[41],"resides":[44],"shift":[46,114],"registers":[47],"as":[48],"sequences":[49,59,85],"`1'":[51],"and":[52,63,106],"`0'":[53],"bits.":[54],"In":[55],"many":[56],"systems,":[57],"these":[58],"are":[60],"too":[61],"long,":[62],"have":[64],"large":[65],"area":[66,112],"overhead.":[67],"This":[68,78],"problem":[69],"indisposes":[70],"implementation":[72],"based":[76],"protocol.":[77],"paper":[79],"proposes":[80],"an":[81],"algorithm":[82,100],"that":[83],"finds":[84],"with":[86,91],"shorter":[87],"lengths":[88],"comparison":[90],"prior":[93],"algorithm.":[94],"On":[95],"synthetic/random":[96],"test":[97],"cases,":[98],"gives":[101],"45%":[102],"reduction":[103,110],"average":[105],"up":[107],"73%":[109],"registers.":[115]},"counts_by_year":[{"year":2015,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}