{"id":"https://openalex.org/W1969693240","doi":"https://doi.org/10.1109/icecs.2010.5724728","title":"VLSI implementation of reconfigurable cells for RFU in embedded processors","display_name":"VLSI implementation of reconfigurable cells for RFU in embedded processors","publication_year":2010,"publication_date":"2010-12-01","ids":{"openalex":"https://openalex.org/W1969693240","doi":"https://doi.org/10.1109/icecs.2010.5724728","mag":"1969693240"},"language":"en","primary_location":{"id":"doi:10.1109/icecs.2010.5724728","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecs.2010.5724728","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 17th IEEE International Conference on Electronics, Circuits and Systems","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"http://hdl.handle.net/2108/24027","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5028297120","display_name":"G.C. Cardarilli","orcid":"https://orcid.org/0000-0002-7444-876X"},"institutions":[{"id":"https://openalex.org/I116067653","display_name":"University of Rome Tor Vergata","ror":"https://ror.org/02p77k626","country_code":"IT","type":"education","lineage":["https://openalex.org/I116067653"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"G.C. Cardarilli","raw_affiliation_strings":["Department of Electronic Engineering, University of Roma Tor Vergata, Rome, Italy","Department of Electronic Engineering, University of Rome Tor Vergata, Via del Politecnico 1, 00133, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronic Engineering, University of Roma Tor Vergata, Rome, Italy","institution_ids":["https://openalex.org/I116067653"]},{"raw_affiliation_string":"Department of Electronic Engineering, University of Rome Tor Vergata, Via del Politecnico 1, 00133, Italy","institution_ids":["https://openalex.org/I116067653"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5063300969","display_name":"Luca Di Nunzio","orcid":"https://orcid.org/0000-0002-4312-7939"},"institutions":[{"id":"https://openalex.org/I116067653","display_name":"University of Rome Tor Vergata","ror":"https://ror.org/02p77k626","country_code":"IT","type":"education","lineage":["https://openalex.org/I116067653"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"L. Di Nunzio","raw_affiliation_strings":["Department of Electronic Engineering, University of Roma Tor Vergata, Rome, Italy","Department of Electronic Engineering, University of Rome Tor Vergata, Via del Politecnico 1, 00133, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronic Engineering, University of Roma Tor Vergata, Rome, Italy","institution_ids":["https://openalex.org/I116067653"]},{"raw_affiliation_string":"Department of Electronic Engineering, University of Rome Tor Vergata, Via del Politecnico 1, 00133, Italy","institution_ids":["https://openalex.org/I116067653"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5048482308","display_name":"Rocco Fazzolari","orcid":"https://orcid.org/0000-0002-7383-2663"},"institutions":[{"id":"https://openalex.org/I116067653","display_name":"University of Rome Tor Vergata","ror":"https://ror.org/02p77k626","country_code":"IT","type":"education","lineage":["https://openalex.org/I116067653"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"R. Fazzolari","raw_affiliation_strings":["Department of Electronic Engineering, University of Roma Tor Vergata, Rome, Italy","Department of Electronic Engineering, University of Rome Tor Vergata, Via del Politecnico 1, 00133, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronic Engineering, University of Roma Tor Vergata, Rome, Italy","institution_ids":["https://openalex.org/I116067653"]},{"raw_affiliation_string":"Department of Electronic Engineering, University of Rome Tor Vergata, Via del Politecnico 1, 00133, Italy","institution_ids":["https://openalex.org/I116067653"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5078795034","display_name":"C. Lenci","orcid":null},"institutions":[{"id":"https://openalex.org/I116067653","display_name":"University of Rome Tor Vergata","ror":"https://ror.org/02p77k626","country_code":"IT","type":"education","lineage":["https://openalex.org/I116067653"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"C. Lenci","raw_affiliation_strings":["Department of Electronic Engineering, University of Roma Tor Vergata, Rome, Italy","Department of Electronic Engineering, University of Rome Tor Vergata, Via del Politecnico 1, 00133, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronic Engineering, University of Roma Tor Vergata, Rome, Italy","institution_ids":["https://openalex.org/I116067653"]},{"raw_affiliation_string":"Department of Electronic Engineering, University of Rome Tor Vergata, Via del Politecnico 1, 00133, Italy","institution_ids":["https://openalex.org/I116067653"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5000963583","display_name":"M. Re","orcid":"https://orcid.org/0000-0001-9046-1318"},"institutions":[{"id":"https://openalex.org/I116067653","display_name":"University of Rome Tor Vergata","ror":"https://ror.org/02p77k626","country_code":"IT","type":"education","lineage":["https://openalex.org/I116067653"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"M. Re","raw_affiliation_strings":["Department of Electronic Engineering, University of Roma Tor Vergata, Rome, Italy","Department of Electronic Engineering, University of Rome Tor Vergata, Via del Politecnico 1, 00133, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronic Engineering, University of Roma Tor Vergata, Rome, Italy","institution_ids":["https://openalex.org/I116067653"]},{"raw_affiliation_string":"Department of Electronic Engineering, University of Rome Tor Vergata, Via del Politecnico 1, 00133, Italy","institution_ids":["https://openalex.org/I116067653"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I116067653"],"apc_list":null,"apc_paid":null,"fwci":0.3131,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.48476145,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"1180","last_page":"1183"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T12162","display_name":"Cellular Automata and Applications","score":0.9980999827384949,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T12162","display_name":"Cellular Automata and Applications","score":0.9980999827384949,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.996399998664856,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9933000206947327,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.8339330554008484},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6739808917045593},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.6362515687942505},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.42964085936546326},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.37084710597991943}],"concepts":[{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.8339330554008484},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6739808917045593},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.6362515687942505},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.42964085936546326},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.37084710597991943}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/icecs.2010.5724728","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecs.2010.5724728","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 17th IEEE International Conference on Electronics, Circuits and Systems","raw_type":"proceedings-article"},{"id":"pmh:oai:art.torvergata.it:2108/24027","is_oa":true,"landing_page_url":"http://hdl.handle.net/2108/24027","pdf_url":null,"source":{"id":"https://openalex.org/S4306400993","display_name":"Cineca Institutional Research Information System (Tor Vergata University)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I116067653","host_organization_name":"University of Rome Tor Vergata","host_organization_lineage":["https://openalex.org/I116067653"],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by-nc-nd","license_id":"https://openalex.org/licenses/cc-by-nc-nd","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"info:eu-repo/semantics/conferenceObject"}],"best_oa_location":{"id":"pmh:oai:art.torvergata.it:2108/24027","is_oa":true,"landing_page_url":"http://hdl.handle.net/2108/24027","pdf_url":null,"source":{"id":"https://openalex.org/S4306400993","display_name":"Cineca Institutional Research Information System (Tor Vergata University)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I116067653","host_organization_name":"University of Rome Tor Vergata","host_organization_lineage":["https://openalex.org/I116067653"],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by-nc-nd","license_id":"https://openalex.org/licenses/cc-by-nc-nd","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"info:eu-repo/semantics/conferenceObject"},"sustainable_development_goals":[{"score":0.8500000238418579,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":5,"referenced_works":["https://openalex.org/W2075000713","https://openalex.org/W2098129944","https://openalex.org/W2128812806","https://openalex.org/W2149307572","https://openalex.org/W6669226597"],"related_works":["https://openalex.org/W4391375266","https://openalex.org/W2748952813","https://openalex.org/W4283025278","https://openalex.org/W2390279801","https://openalex.org/W61292821","https://openalex.org/W2358668433","https://openalex.org/W2082432309","https://openalex.org/W2134640991","https://openalex.org/W3027318491","https://openalex.org/W101478184"],"abstract_inverted_index":{"The":[0],"execution":[1],"of":[2,15,43,53,89,114,127],"operations":[3],"on":[4,27,60,72,122,133],"data":[5],"shorter":[6],"than":[7,102],"the":[8,13,51,76,87,103,115,125],"native":[9],"wordlenght":[10],"usually":[11],"decreases":[12],"performance":[14],"standard":[16],"microprocessors.":[17],"In":[18,63,106],"order":[19],"to":[20,80,136],"overcome":[21],"this":[22,107],"issue,":[23],"various":[24],"methods,":[25],"based":[26,59,71,121],"reconfigurable":[28,45,55,69],"structures,":[29],"have":[30],"been":[31],"presented":[32,66],"in":[33],"literature.":[34],"These":[35],"structures":[36],"are":[37],"normally":[38],"realized":[39],"as":[40],"an":[41,111],"array":[42],"elementary":[44,54],"cells.":[46],"A":[47],"common":[48],"solution":[49],"for":[50,124],"realization":[52],"cells":[56],"is":[57,120],"that":[58],"Look-Up":[61],"Tables.":[62],"[4],":[64],"we":[65,109],"a":[67,73,82],"new":[68,83],"cell":[70],"full":[74],"adder;":[75],"final":[77],"aim":[78],"was":[79],"obtain":[81],"structure":[84],"that,":[85],"paying":[86],"price":[88],"slightly":[90],"reduced":[91],"flexibility,":[92],"requires":[93],"less":[94],"silicon":[95],"area":[96,138],"and":[97,129,132],"power,":[98],"being":[99],"ever":[100],"faster":[101],"\u201ctraditional\u201d":[104],"solution.":[105],"paper,":[108],"present":[110],"exhaustive":[112],"evaluation":[113],"proposed":[116],"cell.":[117],"Our":[118],"analysis":[119],"simulations,":[123],"estimation":[126],"delay":[128],"power":[130],"consumption,":[131],"layout":[134],"design,":[135],"evaluate":[137],"occupancy.":[139]},"counts_by_year":[{"year":2014,"cited_by_count":1}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}