{"id":"https://openalex.org/W2101421299","doi":"https://doi.org/10.1109/icecs.2010.5724464","title":"Process-variation tolerant design techniques for multiphase clock generation","display_name":"Process-variation tolerant design techniques for multiphase clock generation","publication_year":2010,"publication_date":"2010-12-01","ids":{"openalex":"https://openalex.org/W2101421299","doi":"https://doi.org/10.1109/icecs.2010.5724464","mag":"2101421299"},"language":"en","primary_location":{"id":"doi:10.1109/icecs.2010.5724464","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecs.2010.5724464","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 17th IEEE International Conference on Electronics, Circuits and Systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5103508154","display_name":"Manohar Nagaraju","orcid":null},"institutions":[{"id":"https://openalex.org/I223532165","display_name":"University of Utah","ror":"https://ror.org/03r0ha626","country_code":"US","type":"education","lineage":["https://openalex.org/I223532165"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Manohar Nagaraju","raw_affiliation_strings":["University of Utah, Salt Lake City, USA"],"affiliations":[{"raw_affiliation_string":"University of Utah, Salt Lake City, USA","institution_ids":["https://openalex.org/I223532165"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5082148405","display_name":"Wei Wu","orcid":"https://orcid.org/0000-0002-1301-2575"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Wei Wu","raw_affiliation_strings":["Northwestern Polytechnic University, Xi'an, China","Northwestern Polytechnic University, Xi'an,   China"],"affiliations":[{"raw_affiliation_string":"Northwestern Polytechnic University, Xi'an, China","institution_ids":[]},{"raw_affiliation_string":"Northwestern Polytechnic University, Xi'an,   China","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5007079313","display_name":"Cameron T. Charles","orcid":null},"institutions":[{"id":"https://openalex.org/I223532165","display_name":"University of Utah","ror":"https://ror.org/03r0ha626","country_code":"US","type":"education","lineage":["https://openalex.org/I223532165"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Cameron T. Charles","raw_affiliation_strings":["University of Utah, Salt Lake City, USA"],"affiliations":[{"raw_affiliation_string":"University of Utah, Salt Lake City, USA","institution_ids":["https://openalex.org/I223532165"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5103508154"],"corresponding_institution_ids":["https://openalex.org/I223532165"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.15035648,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"102","last_page":"105"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/process-variation","display_name":"Process variation","score":0.7368812561035156},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.6261168122291565},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5886090397834778},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.5453592538833618},{"id":"https://openalex.org/keywords/sizing","display_name":"Sizing","score":0.5188335180282593},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.5158542990684509},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.46686577796936035},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.4379105865955353},{"id":"https://openalex.org/keywords/integrated-circuit-design","display_name":"Integrated circuit design","score":0.43131938576698303},{"id":"https://openalex.org/keywords/delay-locked-loop","display_name":"Delay-locked loop","score":0.42210817337036133},{"id":"https://openalex.org/keywords/loop","display_name":"Loop (graph theory)","score":0.4167994260787964},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.24835684895515442},{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"Phase-locked loop","score":0.19278424978256226},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.16200071573257446},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.16043421626091003},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.15360021591186523},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.11265325546264648},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.10410547256469727}],"concepts":[{"id":"https://openalex.org/C93389723","wikidata":"https://www.wikidata.org/wiki/Q7247313","display_name":"Process variation","level":3,"score":0.7368812561035156},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6261168122291565},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5886090397834778},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.5453592538833618},{"id":"https://openalex.org/C2777767291","wikidata":"https://www.wikidata.org/wiki/Q1080291","display_name":"Sizing","level":2,"score":0.5188335180282593},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.5158542990684509},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.46686577796936035},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.4379105865955353},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.43131938576698303},{"id":"https://openalex.org/C190462668","wikidata":"https://www.wikidata.org/wiki/Q492265","display_name":"Delay-locked loop","level":4,"score":0.42210817337036133},{"id":"https://openalex.org/C184670325","wikidata":"https://www.wikidata.org/wiki/Q512604","display_name":"Loop (graph theory)","level":2,"score":0.4167994260787964},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.24835684895515442},{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.19278424978256226},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.16200071573257446},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.16043421626091003},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.15360021591186523},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.11265325546264648},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.10410547256469727},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C114614502","wikidata":"https://www.wikidata.org/wiki/Q76592","display_name":"Combinatorics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/icecs.2010.5724464","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecs.2010.5724464","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 17th IEEE International Conference on Electronics, Circuits and Systems","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.7599999904632568}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":8,"referenced_works":["https://openalex.org/W1548723951","https://openalex.org/W2005421687","https://openalex.org/W2069169282","https://openalex.org/W2095624237","https://openalex.org/W2098811783","https://openalex.org/W2166826967","https://openalex.org/W2788760024","https://openalex.org/W6674559331"],"related_works":["https://openalex.org/W2898479400","https://openalex.org/W1502047864","https://openalex.org/W2735947162","https://openalex.org/W3149081039","https://openalex.org/W1965937483","https://openalex.org/W2081519689","https://openalex.org/W2080794723","https://openalex.org/W1534698975","https://openalex.org/W2077741953","https://openalex.org/W2976866304"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"the":[3,36,55,73,77,81],"design":[4],"of":[5],"a":[6,45,63],"process-variation":[7],"tolerant":[8],"Delay-Locked":[9],"Loop":[10],"(DLL)":[11],"for":[12],"use":[13],"in":[14,35,62,72,76],"multiphase":[15],"clock":[16],"generation.":[17],"A":[18,58],"transistor":[19],"sizing":[20],"methodology":[21],"to":[22,52,87],"reduce":[23,54],"delay":[24,56,82],"variations":[25],"with":[26],"threshold":[27],"voltage":[28],"(V":[29],"<sub":[30],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[31],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">t</sub>":[32],")":[33],"mismatch":[34,75],"Voltage":[37],"Controlled":[38],"Delay":[39],"Line":[40],"(VCDL)":[41],"is":[42,50],"proposed.":[43],"Additionally,":[44],"new":[46],"digital":[47],"calibration":[48],"scheme":[49],"proposed":[51],"further":[53],"variations.":[57],"DLL":[59],"was":[60],"fabricated":[61],"0.6\u03bcm":[64],"CMOS":[65],"process":[66],"and":[67],"measurement":[68],"results":[69],"indicate":[70],"reduction":[71],"maximum":[74],"timing":[78],"error":[79],"among":[80],"blocks":[83],"from":[84],"40.1ps":[85],"(3.28\u00b0)":[86],"13.44ps":[88],"(1.09\u00b0).":[89]},"counts_by_year":[{"year":2019,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
