{"id":"https://openalex.org/W2162346295","doi":"https://doi.org/10.1109/icecs.2009.5411006","title":"The Amulet chips: Architectural development for asynchronous microprocessors","display_name":"The Amulet chips: Architectural development for asynchronous microprocessors","publication_year":2009,"publication_date":"2009-12-01","ids":{"openalex":"https://openalex.org/W2162346295","doi":"https://doi.org/10.1109/icecs.2009.5411006","mag":"2162346295"},"language":"en","primary_location":{"id":"doi:10.1109/icecs.2009.5411006","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecs.2009.5411006","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5053098822","display_name":"Jim Garside","orcid":"https://orcid.org/0000-0001-8812-4742"},"institutions":[{"id":"https://openalex.org/I28407311","display_name":"University of Manchester","ror":"https://ror.org/027m9bs27","country_code":"GB","type":"education","lineage":["https://openalex.org/I28407311"]}],"countries":["GB"],"is_corresponding":true,"raw_author_name":"J.D. Garside","raw_affiliation_strings":["School of Computer Science, University of Manchester, Institute of Science and Technology, Manchester, UK"],"affiliations":[{"raw_affiliation_string":"School of Computer Science, University of Manchester, Institute of Science and Technology, Manchester, UK","institution_ids":["https://openalex.org/I28407311"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5083177159","display_name":"Steve Furber","orcid":"https://orcid.org/0000-0002-6524-3367"},"institutions":[{"id":"https://openalex.org/I28407311","display_name":"University of Manchester","ror":"https://ror.org/027m9bs27","country_code":"GB","type":"education","lineage":["https://openalex.org/I28407311"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"S.B. Furber","raw_affiliation_strings":["School of Computer Science, University of Manchester, Institute of Science and Technology, Manchester, UK"],"affiliations":[{"raw_affiliation_string":"School of Computer Science, University of Manchester, Institute of Science and Technology, Manchester, UK","institution_ids":["https://openalex.org/I28407311"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5047132316","display_name":"Steve Temple","orcid":null},"institutions":[{"id":"https://openalex.org/I28407311","display_name":"University of Manchester","ror":"https://ror.org/027m9bs27","country_code":"GB","type":"education","lineage":["https://openalex.org/I28407311"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"S. Temple","raw_affiliation_strings":["School of Computer Science, University of Manchester, Institute of Science and Technology, Manchester, UK"],"affiliations":[{"raw_affiliation_string":"School of Computer Science, University of Manchester, Institute of Science and Technology, Manchester, UK","institution_ids":["https://openalex.org/I28407311"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5028364392","display_name":"J.V. Woods","orcid":"https://orcid.org/0000-0002-8945-1881"},"institutions":[{"id":"https://openalex.org/I28407311","display_name":"University of Manchester","ror":"https://ror.org/027m9bs27","country_code":"GB","type":"education","lineage":["https://openalex.org/I28407311"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"J.V. Woods","raw_affiliation_strings":["School of Computer Science, University of Manchester, Institute of Science and Technology, Manchester, UK"],"affiliations":[{"raw_affiliation_string":"School of Computer Science, University of Manchester, Institute of Science and Technology, Manchester, UK","institution_ids":["https://openalex.org/I28407311"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5053098822"],"corresponding_institution_ids":["https://openalex.org/I28407311"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":{"value":0.17878638,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/asynchronous-communication","display_name":"Asynchronous communication","score":0.8416954278945923},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7686957120895386},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6361162662506104},{"id":"https://openalex.org/keywords/microarchitecture","display_name":"Microarchitecture","score":0.5248018503189087},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.502220630645752},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.44661587476730347},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.42916256189346313},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.4125377833843231},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3756416141986847},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.18149426579475403},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.17168673872947693},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.14016833901405334}],"concepts":[{"id":"https://openalex.org/C151319957","wikidata":"https://www.wikidata.org/wiki/Q752739","display_name":"Asynchronous communication","level":2,"score":0.8416954278945923},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7686957120895386},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6361162662506104},{"id":"https://openalex.org/C107598950","wikidata":"https://www.wikidata.org/wiki/Q259864","display_name":"Microarchitecture","level":2,"score":0.5248018503189087},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.502220630645752},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.44661587476730347},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.42916256189346313},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.4125377833843231},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3756416141986847},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.18149426579475403},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.17168673872947693},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.14016833901405334},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0}],"mesh":[],"locations_count":4,"locations":[{"id":"doi:10.1109/icecs.2009.5411006","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecs.2009.5411006","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009)","raw_type":"proceedings-article"},{"id":"pmh:oai:pure.atira.dk:openaire_cris_publications/eb761814-7d1d-4d60-aebb-4a273c215e67","is_oa":false,"landing_page_url":"https://research.manchester.ac.uk/en/publications/eb761814-7d1d-4d60-aebb-4a273c215e67","pdf_url":null,"source":{"id":"https://openalex.org/S4306400662","display_name":"Research Explorer (The University of Manchester)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I28407311","host_organization_name":"University of Manchester","host_organization_lineage":["https://openalex.org/I28407311"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Garside, J D, Furber, S B, Temple, S & Woods, J V 2009, The amulet chips: Architectural development for asynchronous microprocessors. in 2009 16th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2009|IEEE Int. Conf. Electron., Circuits Syst., ICECS. IEEE, USA, pp. 343-346, 2009 16th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2009, Yasmine Hammamet, 1/07/09. https://doi.org/10.1109/ICECS.2009.5411006","raw_type":"info:eu-repo/semantics/publishedVersion"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.684.6915","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.684.6915","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://apt.cs.manchester.ac.uk/ftp/pub/apt/papers/ICECS09.pdf","raw_type":"text"},{"id":"pmh:oai:pure.atira.dk:publications/eb761814-7d1d-4d60-aebb-4a273c215e67","is_oa":false,"landing_page_url":"https://www.research.manchester.ac.uk/portal/en/publications/the-amulet-chips-architectural-development-for-asynchronous-microprocessors(eb761814-7d1d-4d60-aebb-4a273c215e67).html","pdf_url":null,"source":{"id":"https://openalex.org/S4306400662","display_name":"Research Explorer (The University of Manchester)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I28407311","host_organization_name":"University of Manchester","host_organization_lineage":["https://openalex.org/I28407311"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Garside, J D, Furber, S B, Temple, S & Woods, J V 2009, The amulet chips: Architectural development for asynchronous microprocessors. in 2009 16th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2009|IEEE Int. Conf. Electron., Circuits Syst., ICECS. IEEE, USA, pp. 343-346, 2009 16th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2009, Yasmine Hammamet, 1/07/09. https://doi.org/10.1109/ICECS.2009.5411006","raw_type":"info:eu-repo/semantics/publishedVersion"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.8999999761581421,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320320291","display_name":"University of Manchester","ror":"https://ror.org/027m9bs27"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W586368724","https://openalex.org/W1496708548","https://openalex.org/W2126590585","https://openalex.org/W2150054527","https://openalex.org/W2154622477","https://openalex.org/W2489355962","https://openalex.org/W4231905827","https://openalex.org/W4234513283","https://openalex.org/W6678932332","https://openalex.org/W7062389935"],"related_works":["https://openalex.org/W2005635288","https://openalex.org/W2116677773","https://openalex.org/W2155261584","https://openalex.org/W1592982659","https://openalex.org/W2138574009","https://openalex.org/W4230680500","https://openalex.org/W2584231425","https://openalex.org/W2534461193","https://openalex.org/W1547865754","https://openalex.org/W2276000909"],"abstract_inverted_index":{"During":[0],"the":[1,10,16,147,163,177,184,199],"1990s":[2],"a":[3,31,45,217],"series":[4,186],"of":[5,18,187,233],"asynchronous":[6,35,227],"microprocessors":[7,188],"based":[8],"on":[9,193,212],"ARM":[11,200],"architecture":[12,33],"was":[13,22,27,56,151],"developed":[14,182],"at":[15,160],"University":[17],"Manchester.":[19],"The":[20],"objective":[21],"to":[23,29,53,88,121,198],"demonstrate":[24],"that":[25,38,58,126,161],"it":[26,55],"feasible":[28],"implement":[30],"commercial":[32,172],"with":[34,73,94,191],"logic":[36],"and":[37,61,69,90,101,104,129,189,206,231],"certain":[39],"advantages":[40,164],"could":[41,64,70],"be":[42,65,115,133],"gained":[43],"from":[44],"self-timed":[46],"processor.":[47],"By":[48],"carrying":[49],"these":[50],"designs":[51],"through":[52],"silicon":[54],"demonstrated":[57],"processors,":[59,78],"caches":[60],"whole":[62],"systems-on-chip":[63],"built":[66],"without":[67],"clocks":[68],"perform":[71],"competitively":[72],"'conventional',":[74],"synchronous":[75],"systems.":[76],"These":[77,202],"named":[79],"Amulet1-3,":[80],"exhibited":[81],"some":[82],"useful":[83,109],"characteristics,":[84],"particularly":[85,145],"their":[86,102,127,138],"ability":[87],"stop":[89],"start":[91],"almost":[92],"instantaneously":[93],"consequent":[95],"energy":[96,130],"savings":[97],"in":[98,110,146,226],"embedded":[99],"applications":[100],"low-energy":[103],"wide":[105],"spectrum":[106],"electromagnetic":[107],"emission":[108],"wireless":[111],"applications.":[112],"As":[113],"might":[114],"expected":[116],"they":[117],"also":[118],"adapt":[119],"automatically":[120],"supply":[122],"voltage":[123],"variation":[124],"so":[125],"speed":[128],"demands":[131],"may":[132],"regulated":[134],"simply":[135],"by":[136,155,216],"altering":[137],"power":[139],"supply.":[140],"There":[141],"were":[142,165,181],"disadvantages":[143],"too,":[144],"design":[148],"effort":[149],"which":[150,180,195,209],"not":[152,166],"well":[153],"supported":[154],"conventional":[156],"tool":[157],"flows.":[158],"Thus,":[159],"time,":[162],"great":[167],"enough":[168],"for":[169],"any":[170],"widespread":[171],"acceptance.":[173],"This":[174],"paper":[175],"summarises":[176],"architectural":[178],"features":[179],"during":[183],"Amulet":[185],"systems":[190],"emphasis":[192],"mechanisms":[194],"are":[196,229],"non-specific":[197],"architecture.":[201],"include":[203],"register":[204],"forwarding":[205],"cache-line":[207],"fetching":[208],"typically":[210],"rely":[211],"non-local":[213],"synchronisation":[214],"provided":[215],"clock":[218],"signal.":[219],"In":[220],"addition":[221],"deadlocks,":[222],"an":[223],"ever-present":[224],"danger":[225],"systems,":[228],"discussed":[230],"means":[232],"preempting":[234],"them":[235],"presented.":[236]},"counts_by_year":[{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":2},{"year":2017,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}