{"id":"https://openalex.org/W2056989940","doi":"https://doi.org/10.1109/icecs.2009.5410900","title":"Exploring performance-power trade-offs for look-up tables in SRAM-based FPGAs","display_name":"Exploring performance-power trade-offs for look-up tables in SRAM-based FPGAs","publication_year":2009,"publication_date":"2009-12-01","ids":{"openalex":"https://openalex.org/W2056989940","doi":"https://doi.org/10.1109/icecs.2009.5410900","mag":"2056989940"},"language":"en","primary_location":{"id":"doi:10.1109/icecs.2009.5410900","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecs.2009.5410900","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5025250680","display_name":"Pedro Echeverr\u00eda","orcid":null},"institutions":[{"id":"https://openalex.org/I88060688","display_name":"Universidad Polit\u00e9cnica de Madrid","ror":"https://ror.org/03n6nwv02","country_code":"ES","type":"education","lineage":["https://openalex.org/I88060688"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Pedro Echeverria","raw_affiliation_strings":["Department of Electronic Engineering, Universidad Polit\u00e9cnica de Madrid, Spain","Department of Electronic Engineering, Universidad Politecnica de Madrid, Spain"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronic Engineering, Universidad Polit\u00e9cnica de Madrid, Spain","institution_ids":["https://openalex.org/I88060688"]},{"raw_affiliation_string":"Department of Electronic Engineering, Universidad Politecnica de Madrid, Spain","institution_ids":["https://openalex.org/I88060688"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5045572211","display_name":"Marisa L\u00f3pez\u2010Vallejo","orcid":"https://orcid.org/0000-0002-3833-524X"},"institutions":[{"id":"https://openalex.org/I88060688","display_name":"Universidad Polit\u00e9cnica de Madrid","ror":"https://ror.org/03n6nwv02","country_code":"ES","type":"education","lineage":["https://openalex.org/I88060688"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Marisa Lopez-Vallejo","raw_affiliation_strings":["Department of Electronic Engineering, Universidad Polit\u00e9cnica de Madrid, Spain","Department of Electronic Engineering, Universidad Politecnica de Madrid, Spain"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronic Engineering, Universidad Polit\u00e9cnica de Madrid, Spain","institution_ids":["https://openalex.org/I88060688"]},{"raw_affiliation_string":"Department of Electronic Engineering, Universidad Politecnica de Madrid, Spain","institution_ids":["https://openalex.org/I88060688"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5061624015","display_name":"Walter Bolognesi","orcid":null},"institutions":[{"id":"https://openalex.org/I88060688","display_name":"Universidad Polit\u00e9cnica de Madrid","ror":"https://ror.org/03n6nwv02","country_code":"ES","type":"education","lineage":["https://openalex.org/I88060688"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Walter Bolognesi","raw_affiliation_strings":["Department of Electronic Engineering, Universidad Polit\u00e9cnica de Madrid, Spain","Department of Electronic Engineering, Universidad Politecnica de Madrid, Spain"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronic Engineering, Universidad Polit\u00e9cnica de Madrid, Spain","institution_ids":["https://openalex.org/I88060688"]},{"raw_affiliation_string":"Department of Electronic Engineering, Universidad Politecnica de Madrid, Spain","institution_ids":["https://openalex.org/I88060688"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5000478256","display_name":"Carlos Alberto L\u00f3pez Barrio","orcid":"https://orcid.org/0000-0002-2423-5272"},"institutions":[{"id":"https://openalex.org/I88060688","display_name":"Universidad Polit\u00e9cnica de Madrid","ror":"https://ror.org/03n6nwv02","country_code":"ES","type":"education","lineage":["https://openalex.org/I88060688"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Carlos Lopez-Barrio","raw_affiliation_strings":["Department of Electronic Engineering, Universidad Polit\u00e9cnica de Madrid, Spain","Department of Electronic Engineering, Universidad Politecnica de Madrid, Spain"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronic Engineering, Universidad Polit\u00e9cnica de Madrid, Spain","institution_ids":["https://openalex.org/I88060688"]},{"raw_affiliation_string":"Department of Electronic Engineering, Universidad Politecnica de Madrid, Spain","institution_ids":["https://openalex.org/I88060688"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I88060688"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.10648799,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"423","last_page":"426"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/multiplexer","display_name":"Multiplexer","score":0.9059084057807922},{"id":"https://openalex.org/keywords/lookup-table","display_name":"Lookup table","score":0.8555612564086914},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7655409574508667},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7476089000701904},{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.6756196022033691},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.533896803855896},{"id":"https://openalex.org/keywords/reading","display_name":"Reading (process)","score":0.5093258619308472},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.5008704662322998},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.4437715709209442},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4371412694454193},{"id":"https://openalex.org/keywords/multiplexing","display_name":"Multiplexing","score":0.41366010904312134},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3808743357658386},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3591670095920563},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.07030770182609558},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.06169235706329346}],"concepts":[{"id":"https://openalex.org/C70970002","wikidata":"https://www.wikidata.org/wiki/Q189434","display_name":"Multiplexer","level":3,"score":0.9059084057807922},{"id":"https://openalex.org/C134835016","wikidata":"https://www.wikidata.org/wiki/Q690265","display_name":"Lookup table","level":2,"score":0.8555612564086914},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7655409574508667},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7476089000701904},{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.6756196022033691},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.533896803855896},{"id":"https://openalex.org/C554936623","wikidata":"https://www.wikidata.org/wiki/Q199657","display_name":"Reading (process)","level":2,"score":0.5093258619308472},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.5008704662322998},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.4437715709209442},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4371412694454193},{"id":"https://openalex.org/C19275194","wikidata":"https://www.wikidata.org/wiki/Q222903","display_name":"Multiplexing","level":2,"score":0.41366010904312134},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3808743357658386},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3591670095920563},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.07030770182609558},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.06169235706329346},{"id":"https://openalex.org/C17744445","wikidata":"https://www.wikidata.org/wiki/Q36442","display_name":"Political science","level":0,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C199539241","wikidata":"https://www.wikidata.org/wiki/Q7748","display_name":"Law","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/icecs.2009.5410900","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecs.2009.5410900","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":4,"referenced_works":["https://openalex.org/W2013167650","https://openalex.org/W2113645429","https://openalex.org/W2127936519","https://openalex.org/W4241239131"],"related_works":["https://openalex.org/W2039899645","https://openalex.org/W2258948885","https://openalex.org/W2371342700","https://openalex.org/W2327110311","https://openalex.org/W2363059241","https://openalex.org/W2117300767","https://openalex.org/W3215187042","https://openalex.org/W2024574431","https://openalex.org/W1993197222","https://openalex.org/W1972355764"],"abstract_inverted_index":{"Current":[0],"trend":[1],"on":[2,53],"FPGAs":[3],"is":[4,50,86],"to":[5,15,18],"increase":[6],"the":[7,12,28,31,54,81,89],"number":[8],"of":[9,11,30,56],"inputs":[10,17,32],"LUT":[13],"up":[14],"six":[16,75],"improve":[19],"resource":[20],"utilization.":[21],"In":[22],"this":[23],"work":[24],"we":[25],"have":[26],"analyzed":[27],"impact":[29],"expansion":[33],"in":[34],"two":[35],"different":[36],"architectures,":[37],"memory-based":[38,48],"and":[39,44,60,63],"multiplexer-based,":[40],"considering":[41],"area,":[42],"performance":[43],"power.":[45],"A":[46],"new":[47],"architecture":[49,79],"presented":[51],"based":[52],"use":[55],"a":[57,74],"7-transistor":[58],"cell":[59],"dedicated":[61],"reading":[62],"writing":[64],"circuits.":[65],"The":[66],"experimental":[67],"results":[68],"carried":[69],"out":[70],"demonstrate":[71],"that":[72],"for":[73],"input":[76],"LUT,":[77,84],"our":[78],"outperforms":[80],"traditional":[82],"multiplexer-based":[83],"which":[85],"commonly":[87],"considered":[88],"optimum":[90],"architecture.":[91]},"counts_by_year":[{"year":2017,"cited_by_count":1}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}