{"id":"https://openalex.org/W2095986099","doi":"https://doi.org/10.1109/icecs.2009.5410810","title":"Framework for statistical design of a flip-flop","display_name":"Framework for statistical design of a flip-flop","publication_year":2009,"publication_date":"2009-12-01","ids":{"openalex":"https://openalex.org/W2095986099","doi":"https://doi.org/10.1109/icecs.2009.5410810","mag":"2095986099"},"language":"en","primary_location":{"id":"doi:10.1109/icecs.2009.5410810","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecs.2009.5410810","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5071856983","display_name":"Sayed Alireza Sadrossadat","orcid":"https://orcid.org/0000-0002-6192-1167"},"institutions":[{"id":"https://openalex.org/I151746483","display_name":"University of Waterloo","ror":"https://ror.org/01aff2v68","country_code":"CA","type":"education","lineage":["https://openalex.org/I151746483"]}],"countries":["CA"],"is_corresponding":true,"raw_author_name":"Sayed Alireza Sadrossadat","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Waterloo, Waterloo, ONT, Canada","Department of Electrical and computer Engineering, University of Waterloo, ON, N2L 3G1, Canada"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Waterloo, Waterloo, ONT, Canada","institution_ids":["https://openalex.org/I151746483"]},{"raw_affiliation_string":"Department of Electrical and computer Engineering, University of Waterloo, ON, N2L 3G1, Canada","institution_ids":["https://openalex.org/I151746483"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5052452186","display_name":"Minoo Mirsaeedi","orcid":null},"institutions":[{"id":"https://openalex.org/I151746483","display_name":"University of Waterloo","ror":"https://ror.org/01aff2v68","country_code":"CA","type":"education","lineage":["https://openalex.org/I151746483"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Minoo Mirsaeedi","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Waterloo, Waterloo, ONT, Canada","Department of Electrical and computer Engineering, University of Waterloo, ON, N2L 3G1, Canada"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Waterloo, Waterloo, ONT, Canada","institution_ids":["https://openalex.org/I151746483"]},{"raw_affiliation_string":"Department of Electrical and computer Engineering, University of Waterloo, ON, N2L 3G1, Canada","institution_ids":["https://openalex.org/I151746483"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5086032740","display_name":"K. Ponnambalam","orcid":"https://orcid.org/0000-0002-4107-4829"},"institutions":[{"id":"https://openalex.org/I151746483","display_name":"University of Waterloo","ror":"https://ror.org/01aff2v68","country_code":"CA","type":"education","lineage":["https://openalex.org/I151746483"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Kumaraswamy Ponnambalam","raw_affiliation_strings":["Department of Systems Design Engineering, University of Waterloo, Waterloo, ONT, Canada","Department of Systems Design Engineering, University of Waterloo, Canada N2L 3G1"],"affiliations":[{"raw_affiliation_string":"Department of Systems Design Engineering, University of Waterloo, Waterloo, ONT, Canada","institution_ids":["https://openalex.org/I151746483"]},{"raw_affiliation_string":"Department of Systems Design Engineering, University of Waterloo, Canada N2L 3G1","institution_ids":["https://openalex.org/I151746483"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5112829693","display_name":"Mohab Anis","orcid":null},"institutions":[{"id":"https://openalex.org/I151746483","display_name":"University of Waterloo","ror":"https://ror.org/01aff2v68","country_code":"CA","type":"education","lineage":["https://openalex.org/I151746483"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Mohab Anis","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Waterloo, Waterloo, ONT, Canada","Department of Electrical and computer Engineering, University of Waterloo, ON, N2L 3G1, Canada"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Waterloo, Waterloo, ONT, Canada","institution_ids":["https://openalex.org/I151746483"]},{"raw_affiliation_string":"Department of Electrical and computer Engineering, University of Waterloo, ON, N2L 3G1, Canada","institution_ids":["https://openalex.org/I151746483"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5071856983"],"corresponding_institution_ids":["https://openalex.org/I151746483"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.12243555,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"1","issue":null,"first_page":"679","last_page":"682"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9983999729156494,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/flip-flop","display_name":"Flip-flop","score":0.8264303207397461},{"id":"https://openalex.org/keywords/flops","display_name":"FLOPS","score":0.7886060476303101},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.6100174784660339},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6076122522354126},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5409061312675476},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.540368914604187},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5001089572906494},{"id":"https://openalex.org/keywords/sequential-logic","display_name":"Sequential logic","score":0.490075945854187},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.45642632246017456},{"id":"https://openalex.org/keywords/process-variation","display_name":"Process variation","score":0.4269164800643921},{"id":"https://openalex.org/keywords/yield","display_name":"Yield (engineering)","score":0.4173992872238159},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.33083170652389526},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.24687999486923218},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.235835999250412},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.22037962079048157},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.1395595669746399}],"concepts":[{"id":"https://openalex.org/C2781007278","wikidata":"https://www.wikidata.org/wiki/Q183406","display_name":"Flip-flop","level":3,"score":0.8264303207397461},{"id":"https://openalex.org/C3826847","wikidata":"https://www.wikidata.org/wiki/Q188768","display_name":"FLOPS","level":2,"score":0.7886060476303101},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.6100174784660339},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6076122522354126},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5409061312675476},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.540368914604187},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5001089572906494},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.490075945854187},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.45642632246017456},{"id":"https://openalex.org/C93389723","wikidata":"https://www.wikidata.org/wiki/Q7247313","display_name":"Process variation","level":3,"score":0.4269164800643921},{"id":"https://openalex.org/C134121241","wikidata":"https://www.wikidata.org/wiki/Q899301","display_name":"Yield (engineering)","level":2,"score":0.4173992872238159},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.33083170652389526},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.24687999486923218},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.235835999250412},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.22037962079048157},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.1395595669746399},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C191897082","wikidata":"https://www.wikidata.org/wiki/Q11467","display_name":"Metallurgy","level":1,"score":0.0},{"id":"https://openalex.org/C192562407","wikidata":"https://www.wikidata.org/wiki/Q228736","display_name":"Materials science","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/icecs.2009.5410810","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecs.2009.5410810","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.49000000953674316,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":8,"referenced_works":["https://openalex.org/W1973137995","https://openalex.org/W2011778848","https://openalex.org/W2082795641","https://openalex.org/W2109195618","https://openalex.org/W2138706204","https://openalex.org/W2144546750","https://openalex.org/W3103339143","https://openalex.org/W3143002681"],"related_works":["https://openalex.org/W2262031297","https://openalex.org/W2024069812","https://openalex.org/W2733322820","https://openalex.org/W2056378213","https://openalex.org/W2045056374","https://openalex.org/W2298981088","https://openalex.org/W2163601309","https://openalex.org/W2350494013","https://openalex.org/W4298048893","https://openalex.org/W1965850601"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"a":[3,43],"statistical":[4],"framework":[5,44,52],"for":[6,45,78],"the":[7,29,54,57,62,86,96,100],"design":[8,59],"of":[9,32,56,64,69,88,102],"flip-flops":[10],"under":[11],"process":[12,25,103],"variations":[13,26],"in":[14,99],"order":[15],"to":[16,94],"maximize":[17],"their":[18,39],"timing":[19,30,74,97],"yield.":[20],"In":[21],"nanometer":[22],"CMOS":[23],"technologies,":[24],"significantly":[27],"impact":[28],"performance":[31],"sequential":[33],"circuits":[34,48],"which":[35],"may":[36],"eventually":[37],"cause":[38],"malfunction.":[40],"Therefore,":[41],"developing":[42],"designing":[46],"such":[47,71],"is":[49,76],"inevitable.":[50],"Our":[51],"generates":[53],"values":[55],"nominal":[58],"parameters;":[60],"i.e.,":[61],"size":[63],"gates":[65,68],"and":[66],"transmission":[67],"flip-flop":[70],"that":[72],"maximum":[73],"yield":[75,87,98],"achieved":[77],"flip-flops.":[79],"While":[80],"previous":[81],"works":[82],"focused":[83],"on":[84],"improving":[85],"flip-flops,":[89],"less":[90],"research":[91],"was":[92],"done":[93],"improve":[95],"presence":[101],"variations.":[104]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}