{"id":"https://openalex.org/W2039318037","doi":"https://doi.org/10.1109/icecs.2008.4675129","title":"The design of active RC filters for the Analog Front End of IC communication systems","display_name":"The design of active RC filters for the Analog Front End of IC communication systems","publication_year":2008,"publication_date":"2008-08-01","ids":{"openalex":"https://openalex.org/W2039318037","doi":"https://doi.org/10.1109/icecs.2008.4675129","mag":"2039318037"},"language":"en","primary_location":{"id":"doi:10.1109/icecs.2008.4675129","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecs.2008.4675129","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 15th IEEE International Conference on Electronics, Circuits and Systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5017200623","display_name":"G.S. Moschytz","orcid":null},"institutions":[{"id":"https://openalex.org/I13955877","display_name":"Bar-Ilan University","ror":"https://ror.org/03kgsv495","country_code":"IL","type":"education","lineage":["https://openalex.org/I13955877"]}],"countries":["IL"],"is_corresponding":true,"raw_author_name":"George Moschytz","raw_affiliation_strings":["Bar-llan University, Israel","Bar-Ilan Univ., Ramat Gan"],"affiliations":[{"raw_affiliation_string":"Bar-llan University, Israel","institution_ids":["https://openalex.org/I13955877"]},{"raw_affiliation_string":"Bar-Ilan Univ., Ramat Gan","institution_ids":["https://openalex.org/I13955877"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5017200623"],"corresponding_institution_ids":["https://openalex.org/I13955877"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.08994571,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"19","last_page":"20"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9890999794006348,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9890999794006348,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9879999756813049,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.986299991607666,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/active-filter","display_name":"Active filter","score":0.6570292711257935},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6074851155281067},{"id":"https://openalex.org/keywords/filter","display_name":"Filter (signal processing)","score":0.582646906375885},{"id":"https://openalex.org/keywords/signal-flow-graph","display_name":"Signal-flow graph","score":0.5801262855529785},{"id":"https://openalex.org/keywords/analogue-filter","display_name":"Analogue filter","score":0.5546205043792725},{"id":"https://openalex.org/keywords/electronic-filter-topology","display_name":"Electronic filter topology","score":0.5450385808944702},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5419716238975525},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.4900699853897095},{"id":"https://openalex.org/keywords/transfer-function","display_name":"Transfer function","score":0.4710310101509094},{"id":"https://openalex.org/keywords/electronic-filter","display_name":"Electronic filter","score":0.44287368655204773},{"id":"https://openalex.org/keywords/filter-design","display_name":"Filter design","score":0.41751521825790405},{"id":"https://openalex.org/keywords/front-and-back-ends","display_name":"Front and back ends","score":0.41406726837158203},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.38251012563705444},{"id":"https://openalex.org/keywords/prototype-filter","display_name":"Prototype filter","score":0.31708526611328125},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2649877667427063},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.21546277403831482},{"id":"https://openalex.org/keywords/digital-filter","display_name":"Digital filter","score":0.1572069525718689},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.0979151725769043}],"concepts":[{"id":"https://openalex.org/C85899133","wikidata":"https://www.wikidata.org/wiki/Q557211","display_name":"Active filter","level":3,"score":0.6570292711257935},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6074851155281067},{"id":"https://openalex.org/C106131492","wikidata":"https://www.wikidata.org/wiki/Q3072260","display_name":"Filter (signal processing)","level":2,"score":0.582646906375885},{"id":"https://openalex.org/C166501922","wikidata":"https://www.wikidata.org/wiki/Q1786523","display_name":"Signal-flow graph","level":2,"score":0.5801262855529785},{"id":"https://openalex.org/C176046018","wikidata":"https://www.wikidata.org/wiki/Q359205","display_name":"Analogue filter","level":4,"score":0.5546205043792725},{"id":"https://openalex.org/C26441681","wikidata":"https://www.wikidata.org/wiki/Q5358359","display_name":"Electronic filter topology","level":5,"score":0.5450385808944702},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5419716238975525},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.4900699853897095},{"id":"https://openalex.org/C81299745","wikidata":"https://www.wikidata.org/wiki/Q334269","display_name":"Transfer function","level":2,"score":0.4710310101509094},{"id":"https://openalex.org/C132237922","wikidata":"https://www.wikidata.org/wiki/Q327754","display_name":"Electronic filter","level":3,"score":0.44287368655204773},{"id":"https://openalex.org/C22597639","wikidata":"https://www.wikidata.org/wiki/Q5449227","display_name":"Filter design","level":3,"score":0.41751521825790405},{"id":"https://openalex.org/C53016008","wikidata":"https://www.wikidata.org/wiki/Q620167","display_name":"Front and back ends","level":2,"score":0.41406726837158203},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.38251012563705444},{"id":"https://openalex.org/C175742284","wikidata":"https://www.wikidata.org/wiki/Q1415537","display_name":"Prototype filter","level":4,"score":0.31708526611328125},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2649877667427063},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.21546277403831482},{"id":"https://openalex.org/C36390408","wikidata":"https://www.wikidata.org/wiki/Q1163067","display_name":"Digital filter","level":3,"score":0.1572069525718689},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.0979151725769043},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C31972630","wikidata":"https://www.wikidata.org/wiki/Q844240","display_name":"Computer vision","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/icecs.2008.4675129","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecs.2008.4675129","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 15th IEEE International Conference on Electronics, Circuits and Systems","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/4","display_name":"Quality Education","score":0.5299999713897705}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W2357067228","https://openalex.org/W2167803437","https://openalex.org/W2021764720","https://openalex.org/W2349284981","https://openalex.org/W134944350","https://openalex.org/W2081031609","https://openalex.org/W4293095329","https://openalex.org/W1960680100","https://openalex.org/W2096639855","https://openalex.org/W2383167751"],"abstract_inverted_index":{"In":[0,195],"the":[1,7,10,17,20,50,73,96,109,117,125,137,169,174,196,200,210,224,228,235,256,261,273,286,297,345,348,350,359,368],"first":[2,229],"part":[3,40,198,230],"of":[4,9,41,46,66,75,90,111,124,139,180,199,212,223,238,289,299,347,364,371],"this":[5],"tutorial,":[6,201],"concept":[8],"dasiaAnalog":[11],"Front":[12],"Enddasia":[13],"(AFE),":[14],"which":[15,36,94,206,215,219],"is":[16,27,84,119],"interface":[18],"to":[19,105,121,152,190,248,265,356],"real":[21],"world":[22],"in":[23,173,178,227,318,326,333],"most":[24,42,126,232],"IC-system":[25],"chips,":[26],"introduced.":[28],"The":[29,44,156],"course":[30,175],"then":[31,60,80,270,295],"focuses":[32],"on":[33,358,377],"active-RC":[34,130,146,221],"filters":[35,166,222,262,302,366],"constitute":[37],"an":[38],"essential":[39],"AFEs.":[43],"formulation":[45,211],"filter":[47,56,77,142,147,253,327],"specifications":[48],"and":[49,114,128,193,250,329,340,361,373],"basic":[51,88,115],"ideas":[52],"associated":[53],"with":[54,214],"classical":[55,67,140],"approximation":[57,103],"theory":[58],"are":[59,79,134,150,158,176,207,231],"briefly":[61,81],"reviewed.":[62],"Some":[63],"key":[64],"points":[65],"network":[68],"theory,":[69,93],"as":[70,185,303],"needed":[71],"for":[72,136,209,234,255,277,285,336,367],"understanding":[74],"inductorless":[76,145,220,365],"design,":[78],"recalled.":[82],"This":[83],"followed":[85],"by":[86,305],"some":[87,123,315],"concepts":[89],"signal-flow":[91],"graph":[92],"permit":[95],"transition":[97],"from":[98,102,160],"transfer":[99],"function":[100],"(resulting":[101],"theory)":[104],"circuit":[106],"topology.":[107],"After":[108],"review":[110],"these":[112,266,300],"introductory":[113],"concepts,":[116],"stage":[118],"set":[120],"consider":[122],"important":[127],"established":[129],"filter-design":[131],"techniques.":[132],"Examples":[133],"given":[135],"conversion":[138],"LCR":[141],"structures":[143],"into":[144],"circuits":[148,284],"that":[149,321],"amenable":[151],"IC":[153,287],"chip":[154],"design.":[155,279],"examples":[157],"taken":[159],"typical":[161,372],"modern":[162],"communication":[163,375],"systems.":[164],"Finally,":[165,310],"designed":[167,301],"using":[168],"design":[170,288,328,335,360],"techniques":[171],"covered":[172],"compared":[177],"terms":[179],"practical":[181],"performance":[182,298,362],"criteria":[183,213],"such":[184],"thermal":[186],"output":[187],"noise,":[188],"sensitivity":[189],"component":[191],"tolerances,":[192],"tunablity.":[194],"second":[197],"we":[202,216,268,311],"introduce":[203],"analytical":[204],"tools,":[205],"useful":[208],"can":[217],"decide":[218],"kind":[225],"presented":[226],"suitable":[233],"front":[236,258,369],"end":[237,346,370],"mixed-mode":[239],"integrated-circuit":[240,334],"system":[241],"chips.":[242],"These":[243],"tools":[244],"will":[245],"enable":[246],"us":[247],"select":[249],"characterize":[251],"optimum":[252],"realizations":[254],"analog":[257],"end.":[259],"With":[260],"selected":[263],"according":[264],"criteria,":[267],"shall":[269,294,312],"go":[271],"through":[272],"detailed":[274],"steps":[275],"necessary":[276],"their":[278],"They":[280],"represent":[281],"typical,":[282],"well-proven":[283],"active":[290],"RC":[291],"filters.":[292],"We":[293],"check":[296],"obtained":[304],"computer":[306],"simulation":[307],"(e.g.":[308],"PSpice).":[309],"look":[313],"at":[314],"special":[316,331],"situations":[317],"communications":[319],"systems":[320,376],"require":[322],"(i),":[323],"novel":[324],"topologies":[325],"(ii),":[330],"attention":[332],"higher":[337,341],"frequency":[338],"applications":[339],"bit-rate":[342],"communications.":[343],"At":[344],"course,":[349],"student":[351],"should":[352],"be":[353],"well":[354],"prepared":[355],"embark":[357],"evaluation":[363],"emerging":[374],"a":[378],"chip.":[379]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}