{"id":"https://openalex.org/W2149307572","doi":"https://doi.org/10.1109/icecs.2008.4675099","title":"A full-adder based reconfigurable architecture for fine grain applications: ADAPTO","display_name":"A full-adder based reconfigurable architecture for fine grain applications: ADAPTO","publication_year":2008,"publication_date":"2008-08-01","ids":{"openalex":"https://openalex.org/W2149307572","doi":"https://doi.org/10.1109/icecs.2008.4675099","mag":"2149307572"},"language":"en","primary_location":{"id":"doi:10.1109/icecs.2008.4675099","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecs.2008.4675099","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 15th IEEE International Conference on Electronics, Circuits and Systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"http://hdl.handle.net/2108/27078","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5028297120","display_name":"G.C. Cardarilli","orcid":"https://orcid.org/0000-0002-7444-876X"},"institutions":[{"id":"https://openalex.org/I116067653","display_name":"University of Rome Tor Vergata","ror":"https://ror.org/02p77k626","country_code":"IT","type":"education","lineage":["https://openalex.org/I116067653"]}],"countries":["IT"],"is_corresponding":true,"raw_author_name":"G.C. Cardarilli","raw_affiliation_strings":["Department of Electronic Engineering, University of Roma Tor Vergata, Rome, Italy"],"affiliations":[{"raw_affiliation_string":"Department of Electronic Engineering, University of Roma Tor Vergata, Rome, Italy","institution_ids":["https://openalex.org/I116067653"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5063300969","display_name":"Luca Di Nunzio","orcid":"https://orcid.org/0000-0002-4312-7939"},"institutions":[{"id":"https://openalex.org/I116067653","display_name":"University of Rome Tor Vergata","ror":"https://ror.org/02p77k626","country_code":"IT","type":"education","lineage":["https://openalex.org/I116067653"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"L. Di Nunzio","raw_affiliation_strings":["Department of Electronic Engineering, University of Roma Tor Vergata, Rome, Italy"],"affiliations":[{"raw_affiliation_string":"Department of Electronic Engineering, University of Roma Tor Vergata, Rome, Italy","institution_ids":["https://openalex.org/I116067653"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5000963583","display_name":"M. Re","orcid":"https://orcid.org/0000-0001-9046-1318"},"institutions":[{"id":"https://openalex.org/I116067653","display_name":"University of Rome Tor Vergata","ror":"https://ror.org/02p77k626","country_code":"IT","type":"education","lineage":["https://openalex.org/I116067653"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"M. Re","raw_affiliation_strings":["Department of Electronic Engineering, University of Roma Tor Vergata, Rome, Italy"],"affiliations":[{"raw_affiliation_string":"Department of Electronic Engineering, University of Roma Tor Vergata, Rome, Italy","institution_ids":["https://openalex.org/I116067653"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5028297120"],"corresponding_institution_ids":["https://openalex.org/I116067653"],"apc_list":null,"apc_paid":null,"fwci":2.0797,"has_fulltext":false,"cited_by_count":10,"citation_normalized_percentile":{"value":0.88742599,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"1304","last_page":"1307"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9986000061035156,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9986000061035156,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9984999895095825,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9983999729156494,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.8356608152389526},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6793928742408752},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.614942193031311},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.5817769765853882},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.41915053129196167},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3886524736881256},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3594871163368225},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.10765448212623596},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.05974474549293518}],"concepts":[{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.8356608152389526},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6793928742408752},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.614942193031311},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.5817769765853882},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.41915053129196167},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3886524736881256},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3594871163368225},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.10765448212623596},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.05974474549293518},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/icecs.2008.4675099","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecs.2008.4675099","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 15th IEEE International Conference on Electronics, Circuits and Systems","raw_type":"proceedings-article"},{"id":"pmh:oai:art.torvergata.it:2108/27078","is_oa":true,"landing_page_url":"http://hdl.handle.net/2108/27078","pdf_url":null,"source":{"id":"https://openalex.org/S4306400993","display_name":"Cineca Institutional Research Information System (Tor Vergata University)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I116067653","host_organization_name":"University of Rome Tor Vergata","host_organization_lineage":["https://openalex.org/I116067653"],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by-nc-nd","license_id":"https://openalex.org/licenses/cc-by-nc-nd","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"info:eu-repo/semantics/conferenceObject"}],"best_oa_location":{"id":"pmh:oai:art.torvergata.it:2108/27078","is_oa":true,"landing_page_url":"http://hdl.handle.net/2108/27078","pdf_url":null,"source":{"id":"https://openalex.org/S4306400993","display_name":"Cineca Institutional Research Information System (Tor Vergata University)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I116067653","host_organization_name":"University of Rome Tor Vergata","host_organization_lineage":["https://openalex.org/I116067653"],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by-nc-nd","license_id":"https://openalex.org/licenses/cc-by-nc-nd","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"info:eu-repo/semantics/conferenceObject"},"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W1747765598","https://openalex.org/W1882870471","https://openalex.org/W1891709150","https://openalex.org/W2098129944","https://openalex.org/W2148911285","https://openalex.org/W2159126185","https://openalex.org/W4252466729"],"related_works":["https://openalex.org/W4390550886","https://openalex.org/W3217463396","https://openalex.org/W2790557758","https://openalex.org/W2516396101","https://openalex.org/W3204929712","https://openalex.org/W4295102875","https://openalex.org/W2300671402","https://openalex.org/W1967938402","https://openalex.org/W2386041993","https://openalex.org/W1608572506"],"abstract_inverted_index":{"Microprocessor":[0],"and":[1,40,104,122],"DSP":[2],"are":[3],"optimized":[4],"to":[5,52],"perform":[6],"operations":[7,28],"on":[8,29,61,64,77],"data":[9,22,32,39,41],"having":[10],"the":[11,34,116],"same":[12,35],"size":[13],"of":[14,115,133],"native":[15,37],"wordlength.":[16],"Their":[17],"performances":[18],"decrease":[19],"when":[20],"shorter":[21],"must":[23],"be":[24],"processed.":[25],"In":[26,82,125],"fact,":[27],"a":[30,65,70,93,106,130],"short":[31],"have":[33,49],"complexity":[36],"wordlength":[38],"resources":[42],"aren\u2019t":[43],"fully":[44],"exploited.":[45],"Recently":[46],"different":[47],"solutions":[48],"been":[50,59],"proposed":[51],"overcome":[53],"this":[54,126],"problem.":[55],"Great":[56],"attention":[57],"has":[58],"posed":[60],"architectures":[62],"based":[63,76],"main":[66,117],"processor":[67],"supported":[68],"by":[69],"Reconfigurable":[71],"Unit":[72],"(RU)":[73],"-":[74],"typically":[75],"LUTs-":[78],"used":[79],"as":[80],"coprocessor.":[81],"[1]we":[83],"presented":[84],"ADAPTO":[85,134],"(Adder-based":[86],"Dynamic":[87],"Architecture":[88],"for":[89],"Processing":[90],"Tailored":[91],"Operators)":[92],"new":[94],"reconfigurable":[95],"architecture":[96],"that":[97,135],"replacing":[98],"LUTs":[99],"with":[100],"another":[101],"computational":[102],"element":[103],"using":[105],"simplified":[107],"interconnect":[108],"network":[109],"allows,":[110],"in":[111],"one":[112],"clock":[113],"cycle":[114],"microprocessor,":[118],"both":[119],"hardware":[120],"reconfiguration":[121],"instruction":[123],"execution.":[124],"paper":[127],"we":[128],"present":[129],"modified":[131],"version":[132],"achieves":[136],"more":[137],"flexibility.":[138]},"counts_by_year":[{"year":2018,"cited_by_count":2},{"year":2017,"cited_by_count":1},{"year":2014,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}