{"id":"https://openalex.org/W2127298806","doi":"https://doi.org/10.1109/icecs.2008.4674986","title":"Ultra low voltage and, nor and XOR CMOS gates","display_name":"Ultra low voltage and, nor and XOR CMOS gates","publication_year":2008,"publication_date":"2008-08-01","ids":{"openalex":"https://openalex.org/W2127298806","doi":"https://doi.org/10.1109/icecs.2008.4674986","mag":"2127298806"},"language":"en","primary_location":{"id":"doi:10.1109/icecs.2008.4674986","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecs.2008.4674986","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 15th IEEE International Conference on Electronics, Circuits and Systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5103258590","display_name":"Yngvar Berg","orcid":"https://orcid.org/0000-0003-4519-995X"},"institutions":[{"id":"https://openalex.org/I184942183","display_name":"University of Oslo","ror":"https://ror.org/01xtthb56","country_code":"NO","type":"education","lineage":["https://openalex.org/I184942183"]}],"countries":["NO"],"is_corresponding":true,"raw_author_name":"Y. Berg","raw_affiliation_strings":["Department of Informatics, University of Oslo, Oslo, Norway","Dept. of Inf., Univ. of Oslo, Oslo"],"affiliations":[{"raw_affiliation_string":"Department of Informatics, University of Oslo, Oslo, Norway","institution_ids":["https://openalex.org/I184942183"]},{"raw_affiliation_string":"Dept. of Inf., Univ. of Oslo, Oslo","institution_ids":["https://openalex.org/I184942183"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5068390115","display_name":"Omid Mirmotahari","orcid":"https://orcid.org/0009-0003-2821-1088"},"institutions":[{"id":"https://openalex.org/I184942183","display_name":"University of Oslo","ror":"https://ror.org/01xtthb56","country_code":"NO","type":"education","lineage":["https://openalex.org/I184942183"]}],"countries":["NO"],"is_corresponding":false,"raw_author_name":"O. Mirmotahari","raw_affiliation_strings":["Department of Informatics, University of Oslo, Oslo, Norway","Dept. of Inf., Univ. of Oslo, Oslo"],"affiliations":[{"raw_affiliation_string":"Department of Informatics, University of Oslo, Oslo, Norway","institution_ids":["https://openalex.org/I184942183"]},{"raw_affiliation_string":"Dept. of Inf., Univ. of Oslo, Oslo","institution_ids":["https://openalex.org/I184942183"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5026627174","display_name":"Snorre Aunet","orcid":"https://orcid.org/0000-0002-6465-8886"},"institutions":[{"id":"https://openalex.org/I184942183","display_name":"University of Oslo","ror":"https://ror.org/01xtthb56","country_code":"NO","type":"education","lineage":["https://openalex.org/I184942183"]}],"countries":["NO"],"is_corresponding":false,"raw_author_name":"S. Aunet","raw_affiliation_strings":["Department of Informatics, University of Oslo, Oslo, Norway","Dept. of Inf., Univ. of Oslo, Oslo"],"affiliations":[{"raw_affiliation_string":"Department of Informatics, University of Oslo, Oslo, Norway","institution_ids":["https://openalex.org/I184942183"]},{"raw_affiliation_string":"Dept. of Inf., Univ. of Oslo, Oslo","institution_ids":["https://openalex.org/I184942183"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5103258590"],"corresponding_institution_ids":["https://openalex.org/I184942183"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.14421642,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"846","last_page":"849"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/nand-gate","display_name":"NAND gate","score":0.8852814435958862},{"id":"https://openalex.org/keywords/and-or-invert","display_name":"AND-OR-Invert","score":0.8520841002464294},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.7944998741149902},{"id":"https://openalex.org/keywords/xor-gate","display_name":"XOR gate","score":0.7475644946098328},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.731899619102478},{"id":"https://openalex.org/keywords/pass-transistor-logic","display_name":"Pass transistor logic","score":0.5602712035179138},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5264003276824951},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5130742788314819},{"id":"https://openalex.org/keywords/nand-logic","display_name":"NAND logic","score":0.4947187602519989},{"id":"https://openalex.org/keywords/nor-gate","display_name":"NOR gate","score":0.47975027561187744},{"id":"https://openalex.org/keywords/xnor-gate","display_name":"XNOR gate","score":0.45895203948020935},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.38703176379203796},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.36352068185806274},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.29336458444595337},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.2669040262699127},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2531467080116272},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.18465131521224976}],"concepts":[{"id":"https://openalex.org/C124296912","wikidata":"https://www.wikidata.org/wiki/Q575178","display_name":"NAND gate","level":3,"score":0.8852814435958862},{"id":"https://openalex.org/C130126468","wikidata":"https://www.wikidata.org/wiki/Q4652943","display_name":"AND-OR-Invert","level":5,"score":0.8520841002464294},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.7944998741149902},{"id":"https://openalex.org/C28495749","wikidata":"https://www.wikidata.org/wiki/Q155516","display_name":"XOR gate","level":3,"score":0.7475644946098328},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.731899619102478},{"id":"https://openalex.org/C198521697","wikidata":"https://www.wikidata.org/wiki/Q7142438","display_name":"Pass transistor logic","level":4,"score":0.5602712035179138},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5264003276824951},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5130742788314819},{"id":"https://openalex.org/C7234692","wikidata":"https://www.wikidata.org/wiki/Q4116068","display_name":"NAND logic","level":4,"score":0.4947187602519989},{"id":"https://openalex.org/C126445297","wikidata":"https://www.wikidata.org/wiki/Q8065380","display_name":"NOR gate","level":4,"score":0.47975027561187744},{"id":"https://openalex.org/C57684291","wikidata":"https://www.wikidata.org/wiki/Q1336142","display_name":"XNOR gate","level":4,"score":0.45895203948020935},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.38703176379203796},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.36352068185806274},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.29336458444595337},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.2669040262699127},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2531467080116272},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.18465131521224976}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/icecs.2008.4674986","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecs.2008.4674986","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 15th IEEE International Conference on Electronics, Circuits and Systems","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W1566416706","https://openalex.org/W1633471522","https://openalex.org/W1663816628","https://openalex.org/W2004954226","https://openalex.org/W2111719342","https://openalex.org/W2114621701","https://openalex.org/W2121190917","https://openalex.org/W2136174403","https://openalex.org/W2138245782","https://openalex.org/W2160142098","https://openalex.org/W2166243422","https://openalex.org/W2170335526","https://openalex.org/W2539328615"],"related_works":["https://openalex.org/W3200424893","https://openalex.org/W4252985704","https://openalex.org/W2616524835","https://openalex.org/W4246304997","https://openalex.org/W1088417888","https://openalex.org/W2765435638","https://openalex.org/W2146208178","https://openalex.org/W2944454566","https://openalex.org/W2963244787","https://openalex.org/W1966410745"],"abstract_inverted_index":{"In":[0,43],"this":[1],"paper":[2],"we":[3,50],"present":[4,51],"NAND,":[5],"NOR":[6,27,48],"and":[7,26,40,47,56,75],"XOR":[8,58],"gates":[9,28,36,49],"exploiting":[10],"the":[11,31],"ultra":[12],"low-voltage":[13],"(ULV)":[14],"CMOS":[15,39,84],"logic":[16,33],"style":[17],"[1]":[18],"[2].":[19],"There":[20],"are":[21,68],"two":[22,66],"kinds":[23],"of":[24,64],"NAND":[25,46],"available":[29],"using":[30],"ULV":[32,59],"style;":[34],"straightforward":[35],"resembling":[37],"complementary":[38],"threshold":[41],"holdgates.":[42],"addition":[44],"to":[45],"a":[52,71,81],"minority":[53],"three":[54],"gate":[55],"an":[57],"gate.":[60],"The":[61],"electrical":[62],"characteristics":[63],"these":[65],"approaches":[67],"discussed":[69],"with":[70],"focus":[72],"on":[73],"delay":[74],"noise":[76],"margins.":[77],"Simulated":[78],"data":[79],"assuming":[80],"90":[82],"nm":[83],"process":[85],"is":[86],"included.":[87]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}