{"id":"https://openalex.org/W2131498261","doi":"https://doi.org/10.1109/icecs.2008.4674952","title":"Digital implementation of cellular neural networks","display_name":"Digital implementation of cellular neural networks","publication_year":2008,"publication_date":"2008-08-01","ids":{"openalex":"https://openalex.org/W2131498261","doi":"https://doi.org/10.1109/icecs.2008.4674952","mag":"2131498261"},"language":"en","primary_location":{"id":"doi:10.1109/icecs.2008.4674952","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecs.2008.4674952","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 15th IEEE International Conference on Electronics, Circuits and Systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5101895659","display_name":"Ryan Grech","orcid":"https://orcid.org/0000-0002-3819-0730"},"institutions":[{"id":"https://openalex.org/I197854408","display_name":"University of Malta","ror":"https://ror.org/03a62bv60","country_code":"MT","type":"education","lineage":["https://openalex.org/I197854408"]}],"countries":["MT"],"is_corresponding":true,"raw_author_name":"Ryan Grech","raw_affiliation_strings":["Department of Microelectronics Faculty of ICT, University of Malta, Msida, Malta","Dept. of Microelectron., Univ. of Malta, Msida"],"affiliations":[{"raw_affiliation_string":"Department of Microelectronics Faculty of ICT, University of Malta, Msida, Malta","institution_ids":["https://openalex.org/I197854408"]},{"raw_affiliation_string":"Dept. of Microelectron., Univ. of Malta, Msida","institution_ids":["https://openalex.org/I197854408"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5051783142","display_name":"Edward Gatt","orcid":"https://orcid.org/0000-0001-6879-719X"},"institutions":[{"id":"https://openalex.org/I197854408","display_name":"University of Malta","ror":"https://ror.org/03a62bv60","country_code":"MT","type":"education","lineage":["https://openalex.org/I197854408"]}],"countries":["MT"],"is_corresponding":false,"raw_author_name":"Edward Gatt","raw_affiliation_strings":["Department of Microelectronics Faculty of ICT, University of Malta, Msida, Malta","Dept. of Microelectron., Univ. of Malta, Msida"],"affiliations":[{"raw_affiliation_string":"Department of Microelectronics Faculty of ICT, University of Malta, Msida, Malta","institution_ids":["https://openalex.org/I197854408"]},{"raw_affiliation_string":"Dept. of Microelectron., Univ. of Malta, Msida","institution_ids":["https://openalex.org/I197854408"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5033957295","display_name":"Ivan Grech","orcid":"https://orcid.org/0000-0002-3721-0015"},"institutions":[{"id":"https://openalex.org/I197854408","display_name":"University of Malta","ror":"https://ror.org/03a62bv60","country_code":"MT","type":"education","lineage":["https://openalex.org/I197854408"]}],"countries":["MT"],"is_corresponding":false,"raw_author_name":"Ivan Grech","raw_affiliation_strings":["Department of Microelectronics Faculty of ICT, University of Malta, Msida, Malta","Dept. of Microelectron., Univ. of Malta, Msida"],"affiliations":[{"raw_affiliation_string":"Department of Microelectronics Faculty of ICT, University of Malta, Msida, Malta","institution_ids":["https://openalex.org/I197854408"]},{"raw_affiliation_string":"Dept. of Microelectron., Univ. of Malta, Msida","institution_ids":["https://openalex.org/I197854408"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5110698610","display_name":"Joseph Micallef","orcid":null},"institutions":[{"id":"https://openalex.org/I197854408","display_name":"University of Malta","ror":"https://ror.org/03a62bv60","country_code":"MT","type":"education","lineage":["https://openalex.org/I197854408"]}],"countries":["MT"],"is_corresponding":false,"raw_author_name":"Joseph Micallef","raw_affiliation_strings":["Department of Microelectronics Faculty of ICT, University of Malta, Msida, Malta","Dept. of Microelectron., Univ. of Malta, Msida"],"affiliations":[{"raw_affiliation_string":"Department of Microelectronics Faculty of ICT, University of Malta, Msida, Malta","institution_ids":["https://openalex.org/I197854408"]},{"raw_affiliation_string":"Dept. of Microelectron., Univ. of Malta, Msida","institution_ids":["https://openalex.org/I197854408"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5101895659"],"corresponding_institution_ids":["https://openalex.org/I197854408"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.13836875,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"710","last_page":"713"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T12162","display_name":"Cellular Automata and Applications","score":0.9922999739646912,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T12162","display_name":"Cellular Automata and Applications","score":0.9922999739646912,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11347","display_name":"Neural Networks Stability and Synchronization","score":0.9901000261306763,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10320","display_name":"Neural Networks and Applications","score":0.9778000116348267,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8088083267211914},{"id":"https://openalex.org/keywords/robustness","display_name":"Robustness (evolution)","score":0.6699679493904114},{"id":"https://openalex.org/keywords/vhdl","display_name":"VHDL","score":0.656531810760498},{"id":"https://openalex.org/keywords/modular-design","display_name":"Modular design","score":0.6299964785575867},{"id":"https://openalex.org/keywords/cellular-neural-network","display_name":"Cellular neural network","score":0.6241033673286438},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.6025323867797852},{"id":"https://openalex.org/keywords/correctness","display_name":"Correctness","score":0.5425245761871338},{"id":"https://openalex.org/keywords/digital-image-processing","display_name":"Digital image processing","score":0.5209604501724243},{"id":"https://openalex.org/keywords/artificial-neural-network","display_name":"Artificial neural network","score":0.4457279145717621},{"id":"https://openalex.org/keywords/image-processing","display_name":"Image processing","score":0.4356761872768402},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.38327786326408386},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.38055840134620667},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.35635459423065186},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3435819149017334},{"id":"https://openalex.org/keywords/image","display_name":"Image (mathematics)","score":0.21808549761772156},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.19717317819595337},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.12532177567481995}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8088083267211914},{"id":"https://openalex.org/C63479239","wikidata":"https://www.wikidata.org/wiki/Q7353546","display_name":"Robustness (evolution)","level":3,"score":0.6699679493904114},{"id":"https://openalex.org/C36941000","wikidata":"https://www.wikidata.org/wiki/Q209455","display_name":"VHDL","level":3,"score":0.656531810760498},{"id":"https://openalex.org/C101468663","wikidata":"https://www.wikidata.org/wiki/Q1620158","display_name":"Modular design","level":2,"score":0.6299964785575867},{"id":"https://openalex.org/C812465","wikidata":"https://www.wikidata.org/wiki/Q5058375","display_name":"Cellular neural network","level":3,"score":0.6241033673286438},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.6025323867797852},{"id":"https://openalex.org/C55439883","wikidata":"https://www.wikidata.org/wiki/Q360812","display_name":"Correctness","level":2,"score":0.5425245761871338},{"id":"https://openalex.org/C104317675","wikidata":"https://www.wikidata.org/wiki/Q1070689","display_name":"Digital image processing","level":4,"score":0.5209604501724243},{"id":"https://openalex.org/C50644808","wikidata":"https://www.wikidata.org/wiki/Q192776","display_name":"Artificial neural network","level":2,"score":0.4457279145717621},{"id":"https://openalex.org/C9417928","wikidata":"https://www.wikidata.org/wiki/Q1070689","display_name":"Image processing","level":3,"score":0.4356761872768402},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.38327786326408386},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.38055840134620667},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.35635459423065186},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3435819149017334},{"id":"https://openalex.org/C115961682","wikidata":"https://www.wikidata.org/wiki/Q860623","display_name":"Image (mathematics)","level":2,"score":0.21808549761772156},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.19717317819595337},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.12532177567481995},{"id":"https://openalex.org/C104317684","wikidata":"https://www.wikidata.org/wiki/Q7187","display_name":"Gene","level":2,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C185592680","wikidata":"https://www.wikidata.org/wiki/Q2329","display_name":"Chemistry","level":0,"score":0.0},{"id":"https://openalex.org/C55493867","wikidata":"https://www.wikidata.org/wiki/Q7094","display_name":"Biochemistry","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/icecs.2008.4674952","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecs.2008.4674952","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 15th IEEE International Conference on Electronics, Circuits and Systems","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9","score":0.47999998927116394}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W1667647204","https://openalex.org/W2404647514","https://openalex.org/W4247536566","https://openalex.org/W2018477250","https://openalex.org/W3119814709","https://openalex.org/W4241418540","https://openalex.org/W1508895727","https://openalex.org/W2725786787","https://openalex.org/W4283160672","https://openalex.org/W1590965489"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"a":[3,17,27,64,118],"digital":[4,10,51,60,119,128,135],"cellular":[5],"neural":[6],"network":[7],"(CNN)":[8],"for":[9,63,127],"image":[11,129],"processing":[12,37,130],"applications.":[13],"The":[14,111],"CNN":[15,120],"is":[16,53,123],"relatively":[18],"new":[19,42],"field":[20],"in":[21],"this":[22],"research,":[23],"making":[24],"use":[25],"of":[26,30,36,44,98],"high":[28],"degree":[29],"parallelism":[31],"to":[32,56,104,116],"achieve":[33],"higher":[34],"levels":[35],"power":[38],"which":[39,122],"continuously":[40],"paves":[41],"ways":[43],"how":[45],"problems":[46],"can":[47],"be":[48],"tackled.":[49],"A":[50],"architecture":[52,121],"employed":[54],"due":[55],"the":[57,74],"fact":[58],"that":[59,94],"devices":[61],"allow":[62],"very":[65],"robust,":[66],"yet":[67],"simple":[68],"and":[69,108,125],"modular":[70],"design":[71,82,91,113],"while":[72],"at":[73],"same":[75],"time":[76],"maintaining":[77],"established":[78],"performance":[79],"standards.":[80],"Digital":[81],"was":[83],"carried":[84],"out":[85,97],"with":[86],"VHDL":[87],"using":[88],"an":[89],"iterative":[90],"methodology,":[92],"meaning":[93],"only":[95],"one":[96],"several":[99],"building":[100],"blocks":[101],"are":[102],"chosen":[103],"ensure":[105],"optimality,":[106],"robustness":[107],"operational":[109],"correctness.":[110],"main":[112],"objectives":[114],"were":[115],"construct":[117],"fast":[124],"compact":[126],"applications":[131],"like":[132],"next":[133],"generation":[134],"cameras.":[136]},"counts_by_year":[{"year":2017,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
