{"id":"https://openalex.org/W2170692588","doi":"https://doi.org/10.1109/icecs.2008.4674898","title":"A software performance simulation methodology for rapid system architecture exploration","display_name":"A software performance simulation methodology for rapid system architecture exploration","publication_year":2008,"publication_date":"2008-08-01","ids":{"openalex":"https://openalex.org/W2170692588","doi":"https://doi.org/10.1109/icecs.2008.4674898","mag":"2170692588"},"language":"en","primary_location":{"id":"doi:10.1109/icecs.2008.4674898","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecs.2008.4674898","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 15th IEEE International Conference on Electronics, Circuits and Systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5080443370","display_name":"Christoph M. Kirchsteiger","orcid":null},"institutions":[{"id":"https://openalex.org/I4092182","display_name":"Graz University of Technology","ror":"https://ror.org/00d7xrm67","country_code":"AT","type":"education","lineage":["https://openalex.org/I4092182"]}],"countries":["AT"],"is_corresponding":true,"raw_author_name":"Christoph M. Kirchsteiger","raw_affiliation_strings":["Institute for Technical Informatics Graz, University of Technology, Austria"],"affiliations":[{"raw_affiliation_string":"Institute for Technical Informatics Graz, University of Technology, Austria","institution_ids":["https://openalex.org/I4092182"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5049874541","display_name":"Harald Schweitzer","orcid":null},"institutions":[{"id":"https://openalex.org/I4092182","display_name":"Graz University of Technology","ror":"https://ror.org/00d7xrm67","country_code":"AT","type":"education","lineage":["https://openalex.org/I4092182"]}],"countries":["AT"],"is_corresponding":false,"raw_author_name":"Harald Schweitzer","raw_affiliation_strings":["Institute for Technical Informatics Graz, University of Technology, Austria"],"affiliations":[{"raw_affiliation_string":"Institute for Technical Informatics Graz, University of Technology, Austria","institution_ids":["https://openalex.org/I4092182"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5056083251","display_name":"Christoph Trummer","orcid":null},"institutions":[{"id":"https://openalex.org/I4092182","display_name":"Graz University of Technology","ror":"https://ror.org/00d7xrm67","country_code":"AT","type":"education","lineage":["https://openalex.org/I4092182"]}],"countries":["AT"],"is_corresponding":false,"raw_author_name":"Christoph Trummer","raw_affiliation_strings":["Institute for Technical Informatics Graz, University of Technology, Austria"],"affiliations":[{"raw_affiliation_string":"Institute for Technical Informatics Graz, University of Technology, Austria","institution_ids":["https://openalex.org/I4092182"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5048811541","display_name":"Christian Steger","orcid":"https://orcid.org/0000-0002-4441-266X"},"institutions":[{"id":"https://openalex.org/I4092182","display_name":"Graz University of Technology","ror":"https://ror.org/00d7xrm67","country_code":"AT","type":"education","lineage":["https://openalex.org/I4092182"]}],"countries":["AT"],"is_corresponding":false,"raw_author_name":"Christian Steger","raw_affiliation_strings":["Institute for Technical Informatics Graz, University of Technology, Austria"],"affiliations":[{"raw_affiliation_string":"Institute for Technical Informatics Graz, University of Technology, Austria","institution_ids":["https://openalex.org/I4092182"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5111468022","display_name":"Reinhold Wei\u00df","orcid":null},"institutions":[{"id":"https://openalex.org/I4092182","display_name":"Graz University of Technology","ror":"https://ror.org/00d7xrm67","country_code":"AT","type":"education","lineage":["https://openalex.org/I4092182"]}],"countries":["AT"],"is_corresponding":false,"raw_author_name":"Reinhold Weiss","raw_affiliation_strings":["Technische Universitat Graz, Graz, Steiermark, AT"],"affiliations":[{"raw_affiliation_string":"Technische Universitat Graz, Graz, Steiermark, AT","institution_ids":["https://openalex.org/I4092182"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5017927619","display_name":"Markus Pistauer","orcid":null},"institutions":[{"id":"https://openalex.org/I4210161816","display_name":"CISC Semiconductor (Austria)","ror":"https://ror.org/05qq13q49","country_code":"AT","type":"company","lineage":["https://openalex.org/I4210161816"]}],"countries":["AT"],"is_corresponding":false,"raw_author_name":"Markus Pistauer","raw_affiliation_strings":["CISC Semiconductor Design and Consulting GmbH, Klagenfurt, Austria"],"affiliations":[{"raw_affiliation_string":"CISC Semiconductor Design and Consulting GmbH, Klagenfurt, Austria","institution_ids":["https://openalex.org/I4210161816"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":6,"corresponding_author_ids":["https://openalex.org/A5080443370"],"corresponding_institution_ids":["https://openalex.org/I4092182"],"apc_list":null,"apc_paid":null,"fwci":2.0797,"has_fulltext":false,"cited_by_count":10,"citation_normalized_percentile":{"value":0.88999688,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"494","last_page":"497"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10933","display_name":"Real-Time Systems Scheduling","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7862952947616577},{"id":"https://openalex.org/keywords/abstraction","display_name":"Abstraction","score":0.621433675289154},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.5746626257896423},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.5538769364356995},{"id":"https://openalex.org/keywords/set","display_name":"Set (abstract data type)","score":0.5220817923545837},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4826410412788391},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.46812453866004944},{"id":"https://openalex.org/keywords/simulation-software","display_name":"Simulation software","score":0.43827003240585327},{"id":"https://openalex.org/keywords/logic-simulation","display_name":"Logic simulation","score":0.43068158626556396},{"id":"https://openalex.org/keywords/abstraction-layer","display_name":"Abstraction layer","score":0.4200400710105896},{"id":"https://openalex.org/keywords/instruction-set","display_name":"Instruction set","score":0.41419222950935364},{"id":"https://openalex.org/keywords/simulation","display_name":"Simulation","score":0.40437814593315125},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3916794955730438},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.17877644300460815},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.17788264155387878},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.08346801996231079},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.06797832250595093}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7862952947616577},{"id":"https://openalex.org/C124304363","wikidata":"https://www.wikidata.org/wiki/Q673661","display_name":"Abstraction","level":2,"score":0.621433675289154},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.5746626257896423},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.5538769364356995},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.5220817923545837},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4826410412788391},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.46812453866004944},{"id":"https://openalex.org/C91757755","wikidata":"https://www.wikidata.org/wiki/Q11121294","display_name":"Simulation software","level":3,"score":0.43827003240585327},{"id":"https://openalex.org/C64859876","wikidata":"https://www.wikidata.org/wiki/Q173673","display_name":"Logic simulation","level":3,"score":0.43068158626556396},{"id":"https://openalex.org/C147358964","wikidata":"https://www.wikidata.org/wiki/Q1200992","display_name":"Abstraction layer","level":3,"score":0.4200400710105896},{"id":"https://openalex.org/C202491316","wikidata":"https://www.wikidata.org/wiki/Q272683","display_name":"Instruction set","level":2,"score":0.41419222950935364},{"id":"https://openalex.org/C44154836","wikidata":"https://www.wikidata.org/wiki/Q45045","display_name":"Simulation","level":1,"score":0.40437814593315125},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3916794955730438},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.17877644300460815},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.17788264155387878},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.08346801996231079},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.06797832250595093},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C111472728","wikidata":"https://www.wikidata.org/wiki/Q9471","display_name":"Epistemology","level":1,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.0},{"id":"https://openalex.org/C138885662","wikidata":"https://www.wikidata.org/wiki/Q5891","display_name":"Philosophy","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/icecs.2008.4674898","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecs.2008.4674898","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 15th IEEE International Conference on Electronics, Circuits and Systems","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W1993655165","https://openalex.org/W2032094184","https://openalex.org/W2099740052","https://openalex.org/W2114084469","https://openalex.org/W2114123611","https://openalex.org/W2121864144","https://openalex.org/W2167314417","https://openalex.org/W3145196017","https://openalex.org/W3147315126","https://openalex.org/W4242270144","https://openalex.org/W4251840223","https://openalex.org/W4256186103","https://openalex.org/W6792692645"],"related_works":["https://openalex.org/W1984744919","https://openalex.org/W2132930690","https://openalex.org/W2770599040","https://openalex.org/W1901380330","https://openalex.org/W3009812692","https://openalex.org/W2075164989","https://openalex.org/W2901324294","https://openalex.org/W4248324254","https://openalex.org/W3017219868","https://openalex.org/W3117872823"],"abstract_inverted_index":{"The":[0],"performance":[1,16],"simulation":[2,15,42],"of":[3,17],"embedded":[4],"system":[5],"designs":[6],"is":[7,29],"often":[8],"a":[9,33],"time":[10],"consuming":[11],"process.":[12],"Whereas":[13],"the":[14,22,26,40],"hardware":[18],"models":[19],"depends":[20],"on":[21],"chosen":[23],"abstraction":[24],"level,":[25],"software":[27],"part":[28],"usually":[30],"simulated":[31],"with":[32],"slow":[34],"Instruction-Set-Simulator":[35],"(ISS),":[36],"which":[37],"greatly":[38],"limits":[39],"entire":[41],"speed.":[43]},"counts_by_year":[{"year":2020,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
