{"id":"https://openalex.org/W2113211123","doi":"https://doi.org/10.1109/icecs.2008.4674812","title":"Design guidelines for high-speed Transmission-gate latches: Analysis and comparison","display_name":"Design guidelines for high-speed Transmission-gate latches: Analysis and comparison","publication_year":2008,"publication_date":"2008-08-01","ids":{"openalex":"https://openalex.org/W2113211123","doi":"https://doi.org/10.1109/icecs.2008.4674812","mag":"2113211123"},"language":"en","primary_location":{"id":"doi:10.1109/icecs.2008.4674812","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecs.2008.4674812","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 15th IEEE International Conference on Electronics, Circuits and Systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5108433724","display_name":"Gaetano Palumbo","orcid":null},"institutions":[{"id":"https://openalex.org/I39063666","display_name":"University of Catania","ror":"https://ror.org/03a64bh57","country_code":"IT","type":"education","lineage":["https://openalex.org/I39063666"]}],"countries":["IT"],"is_corresponding":true,"raw_author_name":"Gaetano Palumbo","raw_affiliation_strings":["DIEES Dipartimento di Ingegneria Elettrica, Elettronica e dei Sistemi, Universita Catania, Catania, Italy","Dipt. di Ing. Elettr., Elettron. e dei Sist., Univ. of Catania, Catania"],"affiliations":[{"raw_affiliation_string":"DIEES Dipartimento di Ingegneria Elettrica, Elettronica e dei Sistemi, Universita Catania, Catania, Italy","institution_ids":["https://openalex.org/I39063666"]},{"raw_affiliation_string":"Dipt. di Ing. Elettr., Elettron. e dei Sist., Univ. of Catania, Catania","institution_ids":["https://openalex.org/I39063666"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5109218049","display_name":"Melita Pennisi","orcid":null},"institutions":[{"id":"https://openalex.org/I39063666","display_name":"University of Catania","ror":"https://ror.org/03a64bh57","country_code":"IT","type":"education","lineage":["https://openalex.org/I39063666"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Melita Pennisi","raw_affiliation_strings":["DIEES Dipartimento di Ingegneria Elettrica, Elettronica e dei Sistemi, Universita Catania, Catania, Italy","Dipt. di Ing. Elettr., Elettron. e dei Sist., Univ. of Catania, Catania"],"affiliations":[{"raw_affiliation_string":"DIEES Dipartimento di Ingegneria Elettrica, Elettronica e dei Sistemi, Universita Catania, Catania, Italy","institution_ids":["https://openalex.org/I39063666"]},{"raw_affiliation_string":"Dipt. di Ing. Elettr., Elettron. e dei Sist., Univ. of Catania, Catania","institution_ids":["https://openalex.org/I39063666"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5108433724"],"corresponding_institution_ids":["https://openalex.org/I39063666"],"apc_list":null,"apc_paid":null,"fwci":0.3329,"has_fulltext":false,"cited_by_count":12,"citation_normalized_percentile":{"value":0.64980168,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"145","last_page":"148"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6713361144065857},{"id":"https://openalex.org/keywords/powerpc","display_name":"PowerPC","score":0.6289944648742676},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4813600182533264},{"id":"https://openalex.org/keywords/sizing","display_name":"Sizing","score":0.46520620584487915},{"id":"https://openalex.org/keywords/capacitance","display_name":"Capacitance","score":0.45621931552886963},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.44207000732421875},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.4379645884037018},{"id":"https://openalex.org/keywords/transmission-gate","display_name":"Transmission gate","score":0.4292592704296112},{"id":"https://openalex.org/keywords/transmission","display_name":"Transmission (telecommunications)","score":0.4118187427520752},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.2997625768184662},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1842154860496521},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.14818602800369263},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.0926496684551239},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.08198907971382141}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6713361144065857},{"id":"https://openalex.org/C56005371","wikidata":"https://www.wikidata.org/wiki/Q209860","display_name":"PowerPC","level":3,"score":0.6289944648742676},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4813600182533264},{"id":"https://openalex.org/C2777767291","wikidata":"https://www.wikidata.org/wiki/Q1080291","display_name":"Sizing","level":2,"score":0.46520620584487915},{"id":"https://openalex.org/C30066665","wikidata":"https://www.wikidata.org/wiki/Q164399","display_name":"Capacitance","level":3,"score":0.45621931552886963},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.44207000732421875},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.4379645884037018},{"id":"https://openalex.org/C2780949067","wikidata":"https://www.wikidata.org/wiki/Q1136752","display_name":"Transmission gate","level":4,"score":0.4292592704296112},{"id":"https://openalex.org/C761482","wikidata":"https://www.wikidata.org/wiki/Q118093","display_name":"Transmission (telecommunications)","level":2,"score":0.4118187427520752},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.2997625768184662},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1842154860496521},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.14818602800369263},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0926496684551239},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.08198907971382141},{"id":"https://openalex.org/C185592680","wikidata":"https://www.wikidata.org/wiki/Q2329","display_name":"Chemistry","level":0,"score":0.0},{"id":"https://openalex.org/C17525397","wikidata":"https://www.wikidata.org/wiki/Q176140","display_name":"Electrode","level":2,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.0},{"id":"https://openalex.org/C147789679","wikidata":"https://www.wikidata.org/wiki/Q11372","display_name":"Physical chemistry","level":1,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/icecs.2008.4674812","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecs.2008.4674812","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 15th IEEE International Conference on Electronics, Circuits and Systems","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":16,"referenced_works":["https://openalex.org/W2019198721","https://openalex.org/W2046641314","https://openalex.org/W2056378213","https://openalex.org/W2085822974","https://openalex.org/W2088115909","https://openalex.org/W2098988964","https://openalex.org/W2109195618","https://openalex.org/W2128218350","https://openalex.org/W2133484447","https://openalex.org/W2150924088","https://openalex.org/W2164002677","https://openalex.org/W2166316118","https://openalex.org/W3089937351","https://openalex.org/W3143002681","https://openalex.org/W3215015179","https://openalex.org/W4243164749"],"related_works":["https://openalex.org/W2144573411","https://openalex.org/W2384231653","https://openalex.org/W2034971177","https://openalex.org/W2148047679","https://openalex.org/W3166523576","https://openalex.org/W2894516693","https://openalex.org/W2768607109","https://openalex.org/W2136100315","https://openalex.org/W2397249064","https://openalex.org/W2988242922"],"abstract_inverted_index":{"In":[0],"this":[1],"paper":[2],"we":[3],"present":[4],"a":[5,62,74,81],"pencil-and-paper":[6],"procedure":[7,95],"to":[8,30,66,97],"design":[9,99],"transmission-gate":[10],"latches":[11],"for":[12],"high-speed":[13],"performance.":[14],"The":[15,41],"procedure,":[16],"based":[17],"on":[18,73],"the":[19,25,38,50,67,88,93],"Logical":[20],"Effort":[21],"approach,":[22],"independently":[23],"optimizes":[24],"master":[26],"and":[27,87],"slave":[28],"section":[29],"get":[31],"minimum":[32,57],"delay,":[33],"sizing":[34],"all":[35],"transistors":[36,46],"in":[37,49],"critical":[39],"path.":[40],"other":[42,98],"devices,":[43],"like":[44],"keeper":[45],"or":[47],"switches":[48],"positive":[51],"feedback":[52],"networks,":[53],"are":[54,71],"sized":[55],"with":[56,80],"width":[58],"thus":[59],"providing":[60],"only":[61],"negligible":[63],"capacitive":[64],"load":[65],"internal":[68],"nodes.":[69],"Simulations":[70],"performed":[72],"PowerPC":[75],"603":[76],"master-slave":[77],"latch":[78],"designed":[79],"90-nm":[82],"technology":[83],"provided":[84],"by":[85],"STMicroelectronics,":[86],"overall":[89],"good":[90],"performance":[91],"of":[92],"proposed":[94],"compared":[96],"strategies":[100],"is":[101],"verified.":[102]},"counts_by_year":[{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":2},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2014,"cited_by_count":2},{"year":2013,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}