{"id":"https://openalex.org/W2159999145","doi":"https://doi.org/10.1109/icecs.2008.4674810","title":"Analysis of the impact of process variations on static logic circuits versus fan-in","display_name":"Analysis of the impact of process variations on static logic circuits versus fan-in","publication_year":2008,"publication_date":"2008-08-01","ids":{"openalex":"https://openalex.org/W2159999145","doi":"https://doi.org/10.1109/icecs.2008.4674810","mag":"2159999145"},"language":"en","primary_location":{"id":"doi:10.1109/icecs.2008.4674810","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecs.2008.4674810","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 15th IEEE International Conference on Electronics, Circuits and Systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5073077735","display_name":"Massimo Alioto","orcid":null},"institutions":[{"id":"https://openalex.org/I102064193","display_name":"University of Siena","ror":"https://ror.org/01tevnk56","country_code":"IT","type":"education","lineage":["https://openalex.org/I102064193"]}],"countries":["IT"],"is_corresponding":true,"raw_author_name":"Massimo Alioto","raw_affiliation_strings":["DII-Department of Information Engineering, University of Sienna, Siena, Italy"],"affiliations":[{"raw_affiliation_string":"DII-Department of Information Engineering, University of Sienna, Siena, Italy","institution_ids":["https://openalex.org/I102064193"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5044422028","display_name":"G. Palumbo","orcid":"https://orcid.org/0000-0002-8011-8660"},"institutions":[{"id":"https://openalex.org/I39063666","display_name":"University of Catania","ror":"https://ror.org/03a64bh57","country_code":"IT","type":"education","lineage":["https://openalex.org/I39063666"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Gaetano Palumbo","raw_affiliation_strings":["DIEES, Universita Catania, Catania, Italy"],"affiliations":[{"raw_affiliation_string":"DIEES, Universita Catania, Catania, Italy","institution_ids":["https://openalex.org/I39063666"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5109218049","display_name":"Melita Pennisi","orcid":null},"institutions":[{"id":"https://openalex.org/I39063666","display_name":"University of Catania","ror":"https://ror.org/03a64bh57","country_code":"IT","type":"education","lineage":["https://openalex.org/I39063666"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Melita Pennisi","raw_affiliation_strings":["DIEES, Universita Catania, Catania, Italy"],"affiliations":[{"raw_affiliation_string":"DIEES, Universita Catania, Catania, Italy","institution_ids":["https://openalex.org/I39063666"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5073077735"],"corresponding_institution_ids":["https://openalex.org/I102064193"],"apc_list":null,"apc_paid":null,"fwci":0.9988,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.79367496,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"137","last_page":"140"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/fan-in","display_name":"Fan-in","score":0.7092962861061096},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.6739473938941956},{"id":"https://openalex.org/keywords/process-variation","display_name":"Process variation","score":0.6176763772964478},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.6020656824111938},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.5597570538520813},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5566069483757019},{"id":"https://openalex.org/keywords/monte-carlo-method","display_name":"Monte Carlo method","score":0.5553845763206482},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.5421233773231506},{"id":"https://openalex.org/keywords/fan-out","display_name":"Fan-out","score":0.5369524955749512},{"id":"https://openalex.org/keywords/pass-transistor-logic","display_name":"Pass transistor logic","score":0.5210925340652466},{"id":"https://openalex.org/keywords/variation","display_name":"Variation (astronomy)","score":0.5167617201805115},{"id":"https://openalex.org/keywords/delay-calculation","display_name":"Delay calculation","score":0.4806629419326782},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.476046085357666},{"id":"https://openalex.org/keywords/static-timing-analysis","display_name":"Static timing analysis","score":0.47246766090393066},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.4685039818286896},{"id":"https://openalex.org/keywords/propagation-delay","display_name":"Propagation delay","score":0.33098840713500977},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.2741389870643616},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.24487438797950745},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2237248718738556},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.22076889872550964},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.20661720633506775},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.1974019706249237},{"id":"https://openalex.org/keywords/statistics","display_name":"Statistics","score":0.11105737090110779},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.10869261622428894},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.07012602686882019}],"concepts":[{"id":"https://openalex.org/C179431463","wikidata":"https://www.wikidata.org/wiki/Q1760638","display_name":"Fan-in","level":2,"score":0.7092962861061096},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.6739473938941956},{"id":"https://openalex.org/C93389723","wikidata":"https://www.wikidata.org/wiki/Q7247313","display_name":"Process variation","level":3,"score":0.6176763772964478},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.6020656824111938},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.5597570538520813},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5566069483757019},{"id":"https://openalex.org/C19499675","wikidata":"https://www.wikidata.org/wiki/Q232207","display_name":"Monte Carlo method","level":2,"score":0.5553845763206482},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.5421233773231506},{"id":"https://openalex.org/C68812741","wikidata":"https://www.wikidata.org/wiki/Q636609","display_name":"Fan-out","level":3,"score":0.5369524955749512},{"id":"https://openalex.org/C198521697","wikidata":"https://www.wikidata.org/wiki/Q7142438","display_name":"Pass transistor logic","level":4,"score":0.5210925340652466},{"id":"https://openalex.org/C2778334786","wikidata":"https://www.wikidata.org/wiki/Q1586270","display_name":"Variation (astronomy)","level":2,"score":0.5167617201805115},{"id":"https://openalex.org/C174086752","wikidata":"https://www.wikidata.org/wiki/Q5253471","display_name":"Delay calculation","level":3,"score":0.4806629419326782},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.476046085357666},{"id":"https://openalex.org/C93682380","wikidata":"https://www.wikidata.org/wiki/Q2025226","display_name":"Static timing analysis","level":2,"score":0.47246766090393066},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.4685039818286896},{"id":"https://openalex.org/C90806461","wikidata":"https://www.wikidata.org/wiki/Q1144416","display_name":"Propagation delay","level":2,"score":0.33098840713500977},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.2741389870643616},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.24487438797950745},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2237248718738556},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.22076889872550964},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.20661720633506775},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.1974019706249237},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.11105737090110779},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.10869261622428894},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.07012602686882019},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.0},{"id":"https://openalex.org/C44870925","wikidata":"https://www.wikidata.org/wiki/Q37547","display_name":"Astrophysics","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/icecs.2008.4674810","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecs.2008.4674810","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 15th IEEE International Conference on Electronics, Circuits and Systems","raw_type":"proceedings-article"},{"id":"pmh:oai:usiena-air.unisi.it:11365/17299","is_oa":false,"landing_page_url":"http://hdl.handle.net/11365/17299","pdf_url":null,"source":{"id":"https://openalex.org/S4377196319","display_name":"Use Siena air (University of Siena)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I102064193","host_organization_name":"University of Siena","host_organization_lineage":["https://openalex.org/I102064193"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"info:eu-repo/semantics/conferenceObject"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.5699999928474426}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W612784192","https://openalex.org/W655609028","https://openalex.org/W1992544748","https://openalex.org/W2035386754","https://openalex.org/W2097193789","https://openalex.org/W2110033475","https://openalex.org/W2131581217","https://openalex.org/W2134067926","https://openalex.org/W2140823559","https://openalex.org/W2141793803","https://openalex.org/W3103339143","https://openalex.org/W3143002681"],"related_works":["https://openalex.org/W3207923681","https://openalex.org/W4281481227","https://openalex.org/W1990729833","https://openalex.org/W4235695541","https://openalex.org/W2100329931","https://openalex.org/W1804063983","https://openalex.org/W2134944363","https://openalex.org/W2091951595","https://openalex.org/W2542196105","https://openalex.org/W2025241521"],"abstract_inverted_index":{"In":[0,20],"this":[1],"paper,":[2],"the":[3,9,22,32,48,55,72,75,92],"effect":[4,23],"of":[5,11,24,54,57,74],"process":[6,25],"variations":[7,26],"on":[8,78,84],"delay":[10,49,76],"CMOS":[12],"static":[13],"logic":[14],"circuits":[15],"is":[16,34,44],"discussed":[17],"versus":[18],"fan-in.":[19],"particular,":[21],"in":[27],"stacked":[28,58],"transistors":[29,59],"(which":[30],"determine":[31],"fan-in)":[33],"analytically":[35],"evaluated.":[36],"From":[37],"circuit":[38],"analysis,":[39],"a":[40,52,85],"simple":[41],"analytical":[42],"model":[43],"derived":[45],"that":[46],"expresses":[47],"variation":[50,77],"as":[51],"function":[53],"number":[56],"and":[60],"transistor":[61],"size.":[62],"Theoretical":[63],"results":[64],"are":[65],"useful":[66],"to":[67,90],"gain":[68],"an":[69],"insight":[70],"into":[71],"dependence":[73],"design":[79],"parameters.":[80],"Monte":[81],"Carlo":[82],"simulations":[83],"90-nm":[86],"technology":[87],"were":[88],"performed":[89],"validate":[91],"results.":[93]},"counts_by_year":[{"year":2012,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
