{"id":"https://openalex.org/W2097595287","doi":"https://doi.org/10.1109/icecs.2007.4511126","title":"Efficiency Of Components' Region-Constrained Placement To Reduce FPGA's Dynamic Power Consumption","display_name":"Efficiency Of Components' Region-Constrained Placement To Reduce FPGA's Dynamic Power Consumption","publication_year":2007,"publication_date":"2007-12-01","ids":{"openalex":"https://openalex.org/W2097595287","doi":"https://doi.org/10.1109/icecs.2007.4511126","mag":"2097595287"},"language":"en","primary_location":{"id":"doi:10.1109/icecs.2007.4511126","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecs.2007.4511126","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2007 14th IEEE International Conference on Electronics, Circuits and Systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5108813157","display_name":"S. E. Esmaeili","orcid":"https://orcid.org/0000-0001-5912-0865"},"institutions":[{"id":"https://openalex.org/I36721946","display_name":"Kuwait University","ror":"https://ror.org/021e5j056","country_code":"KW","type":"education","lineage":["https://openalex.org/I36721946"]}],"countries":["KW"],"is_corresponding":true,"raw_author_name":"Seyed E. Esmaeili","raw_affiliation_strings":["EE Department, Kuwait University, P.O. Box 5969, Safat 13060, Kuwait","Kuwait Univ., Safat"],"affiliations":[{"raw_affiliation_string":"EE Department, Kuwait University, P.O. Box 5969, Safat 13060, Kuwait","institution_ids":["https://openalex.org/I36721946"]},{"raw_affiliation_string":"Kuwait Univ., Safat","institution_ids":["https://openalex.org/I36721946"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5084652725","display_name":"N.I. Khachab","orcid":null},"institutions":[{"id":"https://openalex.org/I36721946","display_name":"Kuwait University","ror":"https://ror.org/021e5j056","country_code":"KW","type":"education","lineage":["https://openalex.org/I36721946"]}],"countries":["KW"],"is_corresponding":false,"raw_author_name":"Nabil I. Khachab","raw_affiliation_strings":["EE Department, Kuwait University, P.O. Box 5969, Safat 13060, Kuwait. Email: Khachab@eng.kuniv.edu.kw","Kuwait Univ., Safat"],"affiliations":[{"raw_affiliation_string":"EE Department, Kuwait University, P.O. Box 5969, Safat 13060, Kuwait. Email: Khachab@eng.kuniv.edu.kw","institution_ids":["https://openalex.org/I36721946"]},{"raw_affiliation_string":"Kuwait Univ., Safat","institution_ids":["https://openalex.org/I36721946"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5108813157"],"corresponding_institution_ids":["https://openalex.org/I36721946"],"apc_list":null,"apc_paid":null,"fwci":0.357,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.66294857,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"857","last_page":"860"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8212419748306274},{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.6626768708229065},{"id":"https://openalex.org/keywords/multiplexer","display_name":"Multiplexer","score":0.6015110015869141},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5904151201248169},{"id":"https://openalex.org/keywords/virtex","display_name":"Virtex","score":0.5540546178817749},{"id":"https://openalex.org/keywords/dynamic-demand","display_name":"Dynamic demand","score":0.5527825355529785},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.4676131010055542},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.4630691111087799},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.46138954162597656},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.45590680837631226},{"id":"https://openalex.org/keywords/flexibility","display_name":"Flexibility (engineering)","score":0.4322045147418976},{"id":"https://openalex.org/keywords/transistor-count","display_name":"Transistor count","score":0.4175117611885071},{"id":"https://openalex.org/keywords/power-consumption","display_name":"Power consumption","score":0.40044960379600525},{"id":"https://openalex.org/keywords/multiplexing","display_name":"Multiplexing","score":0.12502315640449524},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.11509758234024048},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.10534024238586426},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.07519349455833435}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8212419748306274},{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.6626768708229065},{"id":"https://openalex.org/C70970002","wikidata":"https://www.wikidata.org/wiki/Q189434","display_name":"Multiplexer","level":3,"score":0.6015110015869141},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5904151201248169},{"id":"https://openalex.org/C2777674469","wikidata":"https://www.wikidata.org/wiki/Q20741011","display_name":"Virtex","level":3,"score":0.5540546178817749},{"id":"https://openalex.org/C45872418","wikidata":"https://www.wikidata.org/wiki/Q5318966","display_name":"Dynamic demand","level":3,"score":0.5527825355529785},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.4676131010055542},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.4630691111087799},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.46138954162597656},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.45590680837631226},{"id":"https://openalex.org/C2780598303","wikidata":"https://www.wikidata.org/wiki/Q65921492","display_name":"Flexibility (engineering)","level":2,"score":0.4322045147418976},{"id":"https://openalex.org/C196320899","wikidata":"https://www.wikidata.org/wiki/Q2623746","display_name":"Transistor count","level":4,"score":0.4175117611885071},{"id":"https://openalex.org/C2984118289","wikidata":"https://www.wikidata.org/wiki/Q29954","display_name":"Power consumption","level":3,"score":0.40044960379600525},{"id":"https://openalex.org/C19275194","wikidata":"https://www.wikidata.org/wiki/Q222903","display_name":"Multiplexing","level":2,"score":0.12502315640449524},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.11509758234024048},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.10534024238586426},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.07519349455833435},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/icecs.2007.4511126","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecs.2007.4511126","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2007 14th IEEE International Conference on Electronics, Circuits and Systems","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.8999999761581421}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W1533194083","https://openalex.org/W1906713683","https://openalex.org/W1993072227","https://openalex.org/W2137978438","https://openalex.org/W2155755017","https://openalex.org/W2170510975","https://openalex.org/W4246056576"],"related_works":["https://openalex.org/W2071491930","https://openalex.org/W2900863455","https://openalex.org/W4239403158","https://openalex.org/W2032055818","https://openalex.org/W1984520783","https://openalex.org/W204658489","https://openalex.org/W4234090449","https://openalex.org/W2335991211","https://openalex.org/W4213214900","https://openalex.org/W2090729769"],"abstract_inverted_index":{"The":[0,40],"increased":[1],"flexibility":[2],"offered":[3],"by":[4],"FPGAs":[5,21],"implies":[6],"that":[7],"more":[8],"transistors":[9],"are":[10,82],"needed":[11],"which":[12],"leads":[13],"to":[14],"higher":[15],"power":[16,22,38,61,107,124],"consumption":[17,23,62],"per":[18],"logic":[19,66,115],"gate.":[20],"is":[24,63],"fast":[25],"becoming":[26],"an":[27],"essential":[28],"design":[29],"consideration":[30],"especially":[31],"for":[32,109],"mobile":[33],"systems":[34],"with":[35,87],"a":[36],"limited":[37],"supply.":[39],"effect":[41],"of":[42,75,90,97,113],"components'":[43],"region-constrained":[44,111],"placement":[45],"on":[46,95],"reducing":[47],"internal":[48,57],"nets":[49],"total":[50,59,76],"capacitance":[51],"and":[52,84,104],"the":[53,121],"corresponding":[54],"change":[55],"in":[56],"nets'":[58],"dynamic":[60],"investigated.":[64],"Two":[65],"circuits":[67],"were":[68],"specified":[69],"as":[70],"components":[71,81,92],"covering":[72],"around":[73],"80%":[74],"FPGA":[77],"busy":[78],"gates.":[79],"These":[80],"multiplexers":[83],"adders":[85],"along":[86],"multipliers.":[88],"Each":[89],"these":[91],"was":[93,117],"implemented":[94],"two":[96],"Xilinx":[98,122],"FPGA's":[99],"families,":[100],"namely;":[101],"Spartan":[102],"II":[103],"Virtex.":[105],"Gate-level":[106],"estimation":[108],"different":[110],"placements":[112],"each":[114],"circuit":[116],"carried":[118],"out":[119],"using":[120],"hierarchal":[123],"distribution":[125],"analyzer,":[126],"XPower.":[127]},"counts_by_year":[],"updated_date":"2026-03-20T20:47:17.329874","created_date":"2025-10-10T00:00:00"}