{"id":"https://openalex.org/W1985231829","doi":"https://doi.org/10.1109/icecs.2005.4633599","title":"Considering layout for test scheduling of core-based SoCs","display_name":"Considering layout for test scheduling of core-based SoCs","publication_year":2005,"publication_date":"2005-12-01","ids":{"openalex":"https://openalex.org/W1985231829","doi":"https://doi.org/10.1109/icecs.2005.4633599","mag":"1985231829"},"language":"en","primary_location":{"id":"doi:10.1109/icecs.2005.4633599","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecs.2005.4633599","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2005 12th IEEE International Conference on Electronics, Circuits and Systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5006990756","display_name":"Yu Xia","orcid":"https://orcid.org/0000-0001-7488-0491"},"institutions":[{"id":"https://openalex.org/I126345244","display_name":"Portland State University","ror":"https://ror.org/00yn2fy02","country_code":"US","type":"education","lineage":["https://openalex.org/I126345244"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Yu Xia","raw_affiliation_strings":["Electrical and Computer Engineering, Portland State University, USA","Electr. & Comput. Eng., Portland State Univ., Portland, OR"],"affiliations":[{"raw_affiliation_string":"Electrical and Computer Engineering, Portland State University, USA","institution_ids":["https://openalex.org/I126345244"]},{"raw_affiliation_string":"Electr. & Comput. Eng., Portland State Univ., Portland, OR","institution_ids":["https://openalex.org/I126345244"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5040622659","display_name":"Malgorzata Chrzanowska-Jeske","orcid":"https://orcid.org/0000-0001-5927-1751"},"institutions":[{"id":"https://openalex.org/I126345244","display_name":"Portland State University","ror":"https://ror.org/00yn2fy02","country_code":"US","type":"education","lineage":["https://openalex.org/I126345244"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Malgorzata Chrzanowska-Jeske","raw_affiliation_strings":["Electrical and Computer Engineering, Portland State University, USA","Electr. & Comput. Eng., Portland State Univ., Portland, OR"],"affiliations":[{"raw_affiliation_string":"Electrical and Computer Engineering, Portland State University, USA","institution_ids":["https://openalex.org/I126345244"]},{"raw_affiliation_string":"Electr. & Comput. Eng., Portland State Univ., Portland, OR","institution_ids":["https://openalex.org/I126345244"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5006990756"],"corresponding_institution_ids":["https://openalex.org/I126345244"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.11809099,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9986000061035156,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.992900013923645,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6664753556251526},{"id":"https://openalex.org/keywords/bin-packing-problem","display_name":"Bin packing problem","score":0.6565606594085693},{"id":"https://openalex.org/keywords/scheduling","display_name":"Scheduling (production processes)","score":0.6226950883865356},{"id":"https://openalex.org/keywords/job-shop-scheduling","display_name":"Job shop scheduling","score":0.5181330442428589},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.4937501847743988},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.44950708746910095},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.3679850697517395},{"id":"https://openalex.org/keywords/mathematical-optimization","display_name":"Mathematical optimization","score":0.36691489815711975},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.32840830087661743},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.2584133446216583},{"id":"https://openalex.org/keywords/bin","display_name":"Bin","score":0.22863197326660156},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.174192875623703}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6664753556251526},{"id":"https://openalex.org/C87219788","wikidata":"https://www.wikidata.org/wiki/Q814581","display_name":"Bin packing problem","level":3,"score":0.6565606594085693},{"id":"https://openalex.org/C206729178","wikidata":"https://www.wikidata.org/wiki/Q2271896","display_name":"Scheduling (production processes)","level":2,"score":0.6226950883865356},{"id":"https://openalex.org/C55416958","wikidata":"https://www.wikidata.org/wiki/Q6206757","display_name":"Job shop scheduling","level":3,"score":0.5181330442428589},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.4937501847743988},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.44950708746910095},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.3679850697517395},{"id":"https://openalex.org/C126255220","wikidata":"https://www.wikidata.org/wiki/Q141495","display_name":"Mathematical optimization","level":1,"score":0.36691489815711975},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.32840830087661743},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.2584133446216583},{"id":"https://openalex.org/C156273044","wikidata":"https://www.wikidata.org/wiki/Q4913766","display_name":"Bin","level":2,"score":0.22863197326660156},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.174192875623703},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/icecs.2005.4633599","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecs.2005.4633599","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2005 12th IEEE International Conference on Electronics, Circuits and Systems","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":19,"referenced_works":["https://openalex.org/W1536055443","https://openalex.org/W1596724070","https://openalex.org/W1871184158","https://openalex.org/W2082632465","https://openalex.org/W2097483546","https://openalex.org/W2101924668","https://openalex.org/W2130430551","https://openalex.org/W2131979475","https://openalex.org/W2144473140","https://openalex.org/W2151760281","https://openalex.org/W2157072942","https://openalex.org/W2157999372","https://openalex.org/W2162086806","https://openalex.org/W2165642910","https://openalex.org/W2503952136","https://openalex.org/W4231579915","https://openalex.org/W4236626993","https://openalex.org/W4238437518","https://openalex.org/W6683524346"],"related_works":["https://openalex.org/W2547262947","https://openalex.org/W2060747552","https://openalex.org/W2139517419","https://openalex.org/W2987766391","https://openalex.org/W2371579306","https://openalex.org/W2385645884","https://openalex.org/W4283393550","https://openalex.org/W1972528748","https://openalex.org/W1555842707","https://openalex.org/W3204654320"],"abstract_inverted_index":{"We":[0,70],"consider":[1],"a":[2,18,44,64,68],"test-scheduling":[3,54],"problem,":[4],"with":[5,94],"layout":[6,66],"constraints,":[7],"for":[8,82,87],"core-based":[9],"SOCs.":[10],"Individual":[11],"cores":[12],"have":[13],"to":[14,38],"be":[15],"tested":[16],"on":[17,43],"system":[19],"level":[20],"after":[21],"manufacturing":[22],"and":[23,61,77],"therefore":[24],"special":[25],"test":[26],"access":[27],"mechanisms":[28],"(TAMs)":[29],"are":[30],"required.":[31],"The":[32],"amount":[33],"of":[34,67],"additional":[35],"wires":[36],"needed":[37],"route":[39],"TAMs":[40],"depends":[41],"strongly":[42],"SOC":[45,53],"layout.":[46],"In":[47],"this":[48],"research,":[49],"we":[50],"investigate":[51],"the":[52,58,72],"problem":[55,60,73],"formulated":[56],"as":[57],"bin-packing":[59],"constrained":[62],"by":[63],"physical":[65],"SOC.":[69],"solve":[71],"using":[74],"evolutionary":[75],"strategy":[76],"sequence-pair":[78],"representation.":[79],"Our":[80],"results,":[81],"ITC'02":[83],"benchmarks,":[84],"show":[85],"that":[86],"most":[88],"examples,":[89],"our":[90],"algorithm":[91],"generates":[92],"solutions":[93],"less":[95],"interconnects.":[96]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}