{"id":"https://openalex.org/W1979191935","doi":"https://doi.org/10.1109/icecs.2005.4633590","title":"An algebraic approach for transistor circuit synthesis","display_name":"An algebraic approach for transistor circuit synthesis","publication_year":2005,"publication_date":"2005-12-01","ids":{"openalex":"https://openalex.org/W1979191935","doi":"https://doi.org/10.1109/icecs.2005.4633590","mag":"1979191935"},"language":"en","primary_location":{"id":"doi:10.1109/icecs.2005.4633590","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecs.2005.4633590","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2005 12th IEEE International Conference on Electronics, Circuits and Systems","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5073098982","display_name":"Hiroaki Yoshida","orcid":"https://orcid.org/0000-0002-5370-7451"},"institutions":[{"id":"https://openalex.org/I153327471","display_name":"Bunkyo University","ror":"https://ror.org/053h75930","country_code":"JP","type":"education","lineage":["https://openalex.org/I153327471"]},{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Hiroaki Yoshida","raw_affiliation_strings":["Department of Electronic Engineering, University of Tokyo, 7-3-1 Hongo, Bunkyo-ku, 113-8656, Japan","Department of Electronic Engineering, University of Tokyo, Bunkyo, Tokyo, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronic Engineering, University of Tokyo, 7-3-1 Hongo, Bunkyo-ku, 113-8656, Japan","institution_ids":["https://openalex.org/I153327471","https://openalex.org/I74801974"]},{"raw_affiliation_string":"Department of Electronic Engineering, University of Tokyo, Bunkyo, Tokyo, Japan","institution_ids":["https://openalex.org/I74801974"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5102900006","display_name":"Makoto Ikeda","orcid":"https://orcid.org/0000-0002-6644-4224"},"institutions":[{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Makoto Ikeda","raw_affiliation_strings":["VLSI Design and Education Center(VDEC), University of Tokyo, 7-3-1 Hongo, Bunkyo-ku, 113-8656, Japan","VLSI Design and Education Center (VDEC), University of Tokyo, Bunkyo, Tokyo, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"VLSI Design and Education Center(VDEC), University of Tokyo, 7-3-1 Hongo, Bunkyo-ku, 113-8656, Japan","institution_ids":["https://openalex.org/I74801974"]},{"raw_affiliation_string":"VLSI Design and Education Center (VDEC), University of Tokyo, Bunkyo, Tokyo, Japan","institution_ids":["https://openalex.org/I74801974"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5028680447","display_name":"Kunihiro Asada","orcid":"https://orcid.org/0000-0002-1150-0241"},"institutions":[{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Kunihiro Asada","raw_affiliation_strings":["VLSI Design and Education Center(VDEC), University of Tokyo, 7-3-1 Hongo, Bunkyo-ku, 113-8656, Japan","VLSI Design and Education Center (VDEC), University of Tokyo, Bunkyo, Tokyo, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"VLSI Design and Education Center(VDEC), University of Tokyo, 7-3-1 Hongo, Bunkyo-ku, 113-8656, Japan","institution_ids":["https://openalex.org/I74801974"]},{"raw_affiliation_string":"VLSI Design and Education Center (VDEC), University of Tokyo, Bunkyo, Tokyo, Japan","institution_ids":["https://openalex.org/I74801974"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6608511209487915},{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.6532161235809326},{"id":"https://openalex.org/keywords/graph","display_name":"Graph","score":0.6266522407531738},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.5706505179405212},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.5612735152244568},{"id":"https://openalex.org/keywords/algebraic-number","display_name":"Algebraic number","score":0.4766562581062317},{"id":"https://openalex.org/keywords/suite","display_name":"Suite","score":0.4590069651603699},{"id":"https://openalex.org/keywords/implementation","display_name":"Implementation","score":0.43097788095474243},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.3689206838607788},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.3473239243030548},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.3472026586532593},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.19216156005859375},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.12960141897201538},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.10449987649917603},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.08258190751075745}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6608511209487915},{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.6532161235809326},{"id":"https://openalex.org/C132525143","wikidata":"https://www.wikidata.org/wiki/Q141488","display_name":"Graph","level":2,"score":0.6266522407531738},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.5706505179405212},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.5612735152244568},{"id":"https://openalex.org/C9376300","wikidata":"https://www.wikidata.org/wiki/Q168817","display_name":"Algebraic number","level":2,"score":0.4766562581062317},{"id":"https://openalex.org/C79581498","wikidata":"https://www.wikidata.org/wiki/Q1367530","display_name":"Suite","level":2,"score":0.4590069651603699},{"id":"https://openalex.org/C26713055","wikidata":"https://www.wikidata.org/wiki/Q245962","display_name":"Implementation","level":2,"score":0.43097788095474243},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.3689206838607788},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3473239243030548},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3472026586532593},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.19216156005859375},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.12960141897201538},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.10449987649917603},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.08258190751075745},{"id":"https://openalex.org/C166957645","wikidata":"https://www.wikidata.org/wiki/Q23498","display_name":"Archaeology","level":1,"score":0.0},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0},{"id":"https://openalex.org/C95457728","wikidata":"https://www.wikidata.org/wiki/Q309","display_name":"History","level":0,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/icecs.2005.4633590","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecs.2005.4633590","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2005 12th IEEE International Conference on Electronics, Circuits and Systems","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.301.6417","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.301.6417","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.cad.t.u-tokyo.ac.jp/~hiroaki/papers/yoshida_icecs2005.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W2996288","https://openalex.org/W2003958683","https://openalex.org/W2036887642","https://openalex.org/W2055352363","https://openalex.org/W2063553865","https://openalex.org/W2094923741","https://openalex.org/W2096466247","https://openalex.org/W2169700803","https://openalex.org/W4230970194","https://openalex.org/W4240866746","https://openalex.org/W6600129633","https://openalex.org/W6991201851"],"related_works":["https://openalex.org/W4231704780","https://openalex.org/W2083794993","https://openalex.org/W352609212","https://openalex.org/W1511772879","https://openalex.org/W4379115841","https://openalex.org/W2120447654","https://openalex.org/W2977179488","https://openalex.org/W4200340037","https://openalex.org/W608917066","https://openalex.org/W4283652261"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"an":[3],"algebraic":[4,32],"approach":[5,11,70],"for":[6],"transistor":[7,63],"circuit":[8,20,29],"synthesis.":[9],"Our":[10],"relies":[12],"on":[13,48],"a":[14,41,49,66,72],"graph":[15,36],"structure":[16],"which":[17],"encodes":[18],"multiple":[19],"structural":[21],"configurations.":[22],"The":[23],"proposed":[24,59],"procedure":[25,60],"implicitly":[26],"enumerates":[27],"possible":[28],"configurations":[30],"via":[31],"transformations":[33],"in":[34,71],"the":[35,58],"structure,":[37],"and":[38],"efficiently":[39],"finds":[40],"minimum":[42],"solution":[43],"among":[44],"them.":[45],"Experimental":[46],"results":[47],"benchmark":[50],"suite":[51],"targeting":[52],"standard":[53],"cell":[54],"implementations":[55],"show":[56],"that":[57],"generated":[61],"smaller":[62],"circuits":[64],"than":[65],"technology":[67],"mapping":[68],"based":[69],"comparable":[73],"runtime.":[74]},"counts_by_year":[],"updated_date":"2026-07-22T07:51:19.307946","created_date":"2025-10-10T00:00:00"}
