{"id":"https://openalex.org/W2047154805","doi":"https://doi.org/10.1109/icecs.2005.4633484","title":"Optimization of a fractional-N frequency synthesizer with a VHDL-AMS description using the \"experience plan\" method","display_name":"Optimization of a fractional-N frequency synthesizer with a VHDL-AMS description using the \"experience plan\" method","publication_year":2005,"publication_date":"2005-12-01","ids":{"openalex":"https://openalex.org/W2047154805","doi":"https://doi.org/10.1109/icecs.2005.4633484","mag":"2047154805"},"language":"en","primary_location":{"id":"doi:10.1109/icecs.2005.4633484","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecs.2005.4633484","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2005 12th IEEE International Conference on Electronics, Circuits and Systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5015538402","display_name":"Sonia Eloued","orcid":"https://orcid.org/0000-0002-2928-2430"},"institutions":[{"id":"https://openalex.org/I4210131288","display_name":"National Engineering School of Tunis","ror":"https://ror.org/03b1zjt31","country_code":"TN","type":"education","lineage":["https://openalex.org/I4210131288","https://openalex.org/I63596082"]}],"countries":["TN"],"is_corresponding":true,"raw_author_name":"Sonia Eloued","raw_affiliation_strings":["Laboratory of electronics and technology's information (LETI), National Engineering School of Sfax (ENIS), Tunisia","Nat. Eng. Sch. of Sfax, Lab. of Electron. & Technol.'s Inf. (LETI), Sfax"],"affiliations":[{"raw_affiliation_string":"Laboratory of electronics and technology's information (LETI), National Engineering School of Sfax (ENIS), Tunisia","institution_ids":["https://openalex.org/I4210131288"]},{"raw_affiliation_string":"Nat. Eng. Sch. of Sfax, Lab. of Electron. & Technol.'s Inf. (LETI), Sfax","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5058762615","display_name":"Ahmed Fakhfakh","orcid":"https://orcid.org/0009-0005-3219-2371"},"institutions":[{"id":"https://openalex.org/I4210131288","display_name":"National Engineering School of Tunis","ror":"https://ror.org/03b1zjt31","country_code":"TN","type":"education","lineage":["https://openalex.org/I4210131288","https://openalex.org/I63596082"]}],"countries":["TN"],"is_corresponding":false,"raw_author_name":"Ahmed Fakhfakh","raw_affiliation_strings":["Laboratory of electronics and technology's information (LETI), National Engineering School of Sfax (ENIS), Tunisia","Nat. Eng. Sch. of Sfax, Lab. of Electron. & Technol.'s Inf. (LETI), Sfax"],"affiliations":[{"raw_affiliation_string":"Laboratory of electronics and technology's information (LETI), National Engineering School of Sfax (ENIS), Tunisia","institution_ids":["https://openalex.org/I4210131288"]},{"raw_affiliation_string":"Nat. Eng. Sch. of Sfax, Lab. of Electron. & Technol.'s Inf. (LETI), Sfax","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5109201405","display_name":"Nouri Masmoudi","orcid":null},"institutions":[{"id":"https://openalex.org/I4210131288","display_name":"National Engineering School of Tunis","ror":"https://ror.org/03b1zjt31","country_code":"TN","type":"education","lineage":["https://openalex.org/I4210131288","https://openalex.org/I63596082"]}],"countries":["TN"],"is_corresponding":false,"raw_author_name":"Nouri Masmoudi","raw_affiliation_strings":["Laboratory of electronics and technology's information (LETI), National Engineering School of Sfax (ENIS), Tunisia","Nat. Eng. Sch. of Sfax, Lab. of Electron. & Technol.'s Inf. (LETI), Sfax"],"affiliations":[{"raw_affiliation_string":"Laboratory of electronics and technology's information (LETI), National Engineering School of Sfax (ENIS), Tunisia","institution_ids":["https://openalex.org/I4210131288"]},{"raw_affiliation_string":"Nat. Eng. Sch. of Sfax, Lab. of Electron. & Technol.'s Inf. (LETI), Sfax","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5015538402"],"corresponding_institution_ids":["https://openalex.org/I4210131288"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.1408552,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":"7","issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11444","display_name":"Electromagnetic Compatibility and Noise Suppression","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/vhdl-ams","display_name":"VHDL-AMS","score":0.8370965719223022},{"id":"https://openalex.org/keywords/frequency-synthesizer","display_name":"Frequency synthesizer","score":0.7530102133750916},{"id":"https://openalex.org/keywords/plan","display_name":"Plan (archaeology)","score":0.6293451189994812},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6282187700271606},{"id":"https://openalex.org/keywords/vhdl","display_name":"VHDL","score":0.5673320293426514},{"id":"https://openalex.org/keywords/direct-digital-synthesizer","display_name":"Direct digital synthesizer","score":0.5581026077270508},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4201659858226776},{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"Phase-locked loop","score":0.3464413285255432},{"id":"https://openalex.org/keywords/hardware-description-language","display_name":"Hardware description language","score":0.23860684037208557},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.17659211158752441},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.15631067752838135},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.13153886795043945},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.08887231349945068}],"concepts":[{"id":"https://openalex.org/C2776513426","wikidata":"https://www.wikidata.org/wiki/Q2744740","display_name":"VHDL-AMS","level":4,"score":0.8370965719223022},{"id":"https://openalex.org/C182099602","wikidata":"https://www.wikidata.org/wiki/Q2660678","display_name":"Frequency synthesizer","level":4,"score":0.7530102133750916},{"id":"https://openalex.org/C2776505523","wikidata":"https://www.wikidata.org/wiki/Q4785468","display_name":"Plan (archaeology)","level":2,"score":0.6293451189994812},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6282187700271606},{"id":"https://openalex.org/C36941000","wikidata":"https://www.wikidata.org/wiki/Q209455","display_name":"VHDL","level":3,"score":0.5673320293426514},{"id":"https://openalex.org/C166089067","wikidata":"https://www.wikidata.org/wiki/Q1227465","display_name":"Direct digital synthesizer","level":5,"score":0.5581026077270508},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4201659858226776},{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.3464413285255432},{"id":"https://openalex.org/C42143788","wikidata":"https://www.wikidata.org/wiki/Q173341","display_name":"Hardware description language","level":3,"score":0.23860684037208557},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.17659211158752441},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.15631067752838135},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.13153886795043945},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.08887231349945068},{"id":"https://openalex.org/C95457728","wikidata":"https://www.wikidata.org/wiki/Q309","display_name":"History","level":0,"score":0.0},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.0},{"id":"https://openalex.org/C166957645","wikidata":"https://www.wikidata.org/wiki/Q23498","display_name":"Archaeology","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/icecs.2005.4633484","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecs.2005.4633484","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2005 12th IEEE International Conference on Electronics, Circuits and Systems","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":2,"referenced_works":["https://openalex.org/W2158416277","https://openalex.org/W2189164993"],"related_works":["https://openalex.org/W2350523680","https://openalex.org/W2359104853","https://openalex.org/W2368975962","https://openalex.org/W2374761771","https://openalex.org/W2389258116","https://openalex.org/W2390006665","https://openalex.org/W2117349133","https://openalex.org/W1975162792","https://openalex.org/W2384337837","https://openalex.org/W2167604670"],"abstract_inverted_index":{"In":[0],"this":[1],"paper,":[2],"an":[3],"optimization":[4],"method":[5],"using":[6,30],"\"experience":[7,22],"plan\"":[8,23],"is":[9,24],"applied":[10,25],"to":[11,36],"optimize":[12],"a":[13,27],"fractional-N":[14],"frequency":[15],"synthesizer's":[16],"performances":[17],"for":[18],"wireless":[19],"systems.":[20],"The":[21],"on":[26],"VHDLAMS":[28],"description":[29],"seven":[31],"parameters":[32],"having":[33],"in":[34],"view":[35],"minimize":[37],"the":[38,43],"loop":[39],"response":[40],"time":[41],"and":[42],"synthesizer":[44],"output":[45],"frequency.":[46]},"counts_by_year":[{"year":2019,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
