{"id":"https://openalex.org/W2084207209","doi":"https://doi.org/10.1109/icecs.2005.4633373","title":"1.6-GHz low power low phase noise quadrature phase locked loop with on chip DC-DC converter for wide tuning range","display_name":"1.6-GHz low power low phase noise quadrature phase locked loop with on chip DC-DC converter for wide tuning range","publication_year":2005,"publication_date":"2005-12-01","ids":{"openalex":"https://openalex.org/W2084207209","doi":"https://doi.org/10.1109/icecs.2005.4633373","mag":"2084207209"},"language":"en","primary_location":{"id":"doi:10.1109/icecs.2005.4633373","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecs.2005.4633373","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2005 12th IEEE International Conference on Electronics, Circuits and Systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5044810941","display_name":"Owen Casha","orcid":"https://orcid.org/0000-0002-4337-5609"},"institutions":[{"id":"https://openalex.org/I197854408","display_name":"University of Malta","ror":"https://ror.org/03a62bv60","country_code":"MT","type":"education","lineage":["https://openalex.org/I197854408"]}],"countries":["MT"],"is_corresponding":true,"raw_author_name":"Owen Casha","raw_affiliation_strings":["Department of Microelectronics, University of Malta, Msida, Malta","Dept. of Microelectron., Univ. of Malta, Msida"],"affiliations":[{"raw_affiliation_string":"Department of Microelectronics, University of Malta, Msida, Malta","institution_ids":["https://openalex.org/I197854408"]},{"raw_affiliation_string":"Dept. of Microelectron., Univ. of Malta, Msida","institution_ids":["https://openalex.org/I197854408"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5033957295","display_name":"Ivan Grech","orcid":"https://orcid.org/0000-0002-3721-0015"},"institutions":[{"id":"https://openalex.org/I197854408","display_name":"University of Malta","ror":"https://ror.org/03a62bv60","country_code":"MT","type":"education","lineage":["https://openalex.org/I197854408"]}],"countries":["MT"],"is_corresponding":false,"raw_author_name":"Ivan Grech","raw_affiliation_strings":["Department of Microelectronics, University of Malta, Msida, Malta","Dept. of Microelectron., Univ. of Malta, Msida"],"affiliations":[{"raw_affiliation_string":"Department of Microelectronics, University of Malta, Msida, Malta","institution_ids":["https://openalex.org/I197854408"]},{"raw_affiliation_string":"Dept. of Microelectron., Univ. of Malta, Msida","institution_ids":["https://openalex.org/I197854408"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5051783142","display_name":"Edward Gatt","orcid":"https://orcid.org/0000-0001-6879-719X"},"institutions":[{"id":"https://openalex.org/I197854408","display_name":"University of Malta","ror":"https://ror.org/03a62bv60","country_code":"MT","type":"education","lineage":["https://openalex.org/I197854408"]}],"countries":["MT"],"is_corresponding":false,"raw_author_name":"Edward Gatt","raw_affiliation_strings":["Department of Microelectronics, University of Malta, Msida, Malta","Dept. of Microelectron., Univ. of Malta, Msida"],"affiliations":[{"raw_affiliation_string":"Department of Microelectronics, University of Malta, Msida, Malta","institution_ids":["https://openalex.org/I197854408"]},{"raw_affiliation_string":"Dept. of Microelectron., Univ. of Malta, Msida","institution_ids":["https://openalex.org/I197854408"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5110698610","display_name":"Joseph Micallef","orcid":null},"institutions":[{"id":"https://openalex.org/I197854408","display_name":"University of Malta","ror":"https://ror.org/03a62bv60","country_code":"MT","type":"education","lineage":["https://openalex.org/I197854408"]}],"countries":["MT"],"is_corresponding":false,"raw_author_name":"Joseph Micallef","raw_affiliation_strings":["Department of Microelectronics, University of Malta, Msida, Malta","Dept. of Microelectron., Univ. of Malta, Msida"],"affiliations":[{"raw_affiliation_string":"Department of Microelectronics, University of Malta, Msida, Malta","institution_ids":["https://openalex.org/I197854408"]},{"raw_affiliation_string":"Dept. of Microelectron., Univ. of Malta, Msida","institution_ids":["https://openalex.org/I197854408"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5044810941"],"corresponding_institution_ids":["https://openalex.org/I197854408"],"apc_list":null,"apc_paid":null,"fwci":0.7114,"has_fulltext":false,"cited_by_count":6,"citation_normalized_percentile":{"value":0.73902304,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":96},"biblio":{"volume":"40","issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/dbc","display_name":"dBc","score":0.8908941745758057},{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"Phase-locked loop","score":0.7172264456748962},{"id":"https://openalex.org/keywords/phase-noise","display_name":"Phase noise","score":0.7106355428695679},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.5425248146057129},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.513396143913269},{"id":"https://openalex.org/keywords/offset","display_name":"Offset (computer science)","score":0.511790931224823},{"id":"https://openalex.org/keywords/dc-bias","display_name":"DC bias","score":0.46763160824775696},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.46740347146987915},{"id":"https://openalex.org/keywords/charge-pump","display_name":"Charge pump","score":0.4585009515285492},{"id":"https://openalex.org/keywords/quadrature","display_name":"Quadrature (astronomy)","score":0.4318104386329651},{"id":"https://openalex.org/keywords/delay-locked-loop","display_name":"Delay-locked loop","score":0.4303519129753113},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.41792532801628113},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.3290305435657501},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.30143535137176514},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.21242836117744446},{"id":"https://openalex.org/keywords/capacitor","display_name":"Capacitor","score":0.13303297758102417}],"concepts":[{"id":"https://openalex.org/C193523891","wikidata":"https://www.wikidata.org/wiki/Q1771950","display_name":"dBc","level":3,"score":0.8908941745758057},{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.7172264456748962},{"id":"https://openalex.org/C89631360","wikidata":"https://www.wikidata.org/wiki/Q1428766","display_name":"Phase noise","level":2,"score":0.7106355428695679},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.5425248146057129},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.513396143913269},{"id":"https://openalex.org/C175291020","wikidata":"https://www.wikidata.org/wiki/Q1156822","display_name":"Offset (computer science)","level":2,"score":0.511790931224823},{"id":"https://openalex.org/C88682704","wikidata":"https://www.wikidata.org/wiki/Q2907415","display_name":"DC bias","level":3,"score":0.46763160824775696},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.46740347146987915},{"id":"https://openalex.org/C114825011","wikidata":"https://www.wikidata.org/wiki/Q440704","display_name":"Charge pump","level":4,"score":0.4585009515285492},{"id":"https://openalex.org/C62869609","wikidata":"https://www.wikidata.org/wiki/Q28137","display_name":"Quadrature (astronomy)","level":2,"score":0.4318104386329651},{"id":"https://openalex.org/C190462668","wikidata":"https://www.wikidata.org/wiki/Q492265","display_name":"Delay-locked loop","level":4,"score":0.4303519129753113},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.41792532801628113},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.3290305435657501},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.30143535137176514},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.21242836117744446},{"id":"https://openalex.org/C52192207","wikidata":"https://www.wikidata.org/wiki/Q5322","display_name":"Capacitor","level":3,"score":0.13303297758102417},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/icecs.2005.4633373","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecs.2005.4633373","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2005 12th IEEE International Conference on Electronics, Circuits and Systems","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.8500000238418579,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W1569638374","https://openalex.org/W1668923173","https://openalex.org/W1944261027","https://openalex.org/W2032865504","https://openalex.org/W2033908335","https://openalex.org/W2108370022","https://openalex.org/W2111105786","https://openalex.org/W2117413393","https://openalex.org/W2138134203","https://openalex.org/W2157476064"],"related_works":["https://openalex.org/W66112532","https://openalex.org/W2372909716","https://openalex.org/W2049525097","https://openalex.org/W2012676707","https://openalex.org/W2979324006","https://openalex.org/W2409831949","https://openalex.org/W2087564251","https://openalex.org/W3177439118","https://openalex.org/W4385624389","https://openalex.org/W2119216036"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"the":[3,42,67,83,96,103],"design":[4,99,110],"of":[5,21,28,36,55,63,95],"a":[6,18,26,51],"1.6":[7],"GHz":[8,46,49],"quadrature":[9,38],"phase":[10,52,90],"locked":[11,39],"loop":[12],"for":[13],"GPS":[14],"applications,":[15],"operated":[16],"with":[17,50,86],"supply":[19],"voltage":[20],"1.2":[22],"V":[23],"and":[24,92],"dissipating":[25],"current":[27],"less":[29,56],"than":[30,57],"5":[31],"mA.":[32],"It":[33],"is":[34,73],"capable":[35],"delivering":[37],"signals":[40],"in":[41],"range":[43,72],"from":[44,66],"1.22":[45],"to":[47],"1.96":[48],"noise":[53,91],"response":[54],"-115":[58],"dBc":[59],"at":[60],"an":[61,76],"offset":[62],"1":[64],"MHz":[65],"carrier.":[68],"The":[69,98],"wide":[70],"tuning":[71],"obtained":[74],"using":[75,102],"on-chip":[77],"regulated":[78],"DC-DC":[79],"converter":[80],"clocked":[81],"by":[82],"reference":[84],"signal,":[85],"negligible":[87],"effect":[88],"on":[89],"spurious":[93],"level":[94],"PLL.":[97],"was":[100],"made":[101],"STMicroelectronics":[104],"proprietary":[105],"0.13":[106],"\u03bcm":[107],"HCMOS9":[108],"technology":[109],"kit.":[111]},"counts_by_year":[{"year":2017,"cited_by_count":2},{"year":2016,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
