{"id":"https://openalex.org/W2112814021","doi":"https://doi.org/10.1109/icecs.2004.1399753","title":"Advanced timing of level-sensitive sequential circuits","display_name":"Advanced timing of level-sensitive sequential circuits","publication_year":2005,"publication_date":"2005-03-31","ids":{"openalex":"https://openalex.org/W2112814021","doi":"https://doi.org/10.1109/icecs.2004.1399753","mag":"2112814021"},"language":"en","primary_location":{"id":"doi:10.1109/icecs.2004.1399753","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecs.2004.1399753","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2004 11th IEEE International Conference on Electronics, Circuits and Systems, 2004. ICECS 2004.","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5081080799","display_name":"Bar\u0131\u015f Ta\u015fk\u0131n","orcid":"https://orcid.org/0000-0002-7631-5696"},"institutions":[{"id":"https://openalex.org/I170201317","display_name":"University of Pittsburgh","ror":"https://ror.org/01an3r305","country_code":"US","type":"education","lineage":["https://openalex.org/I170201317"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"B. Taskin","raw_affiliation_strings":["Electrical and Computer Engineering Department, University of Pittsburgh, Pittsburgh, PA, USA","Electr. & Comput. Eng. Dept., Univ. of Pittsburgh, PA, USA"],"affiliations":[{"raw_affiliation_string":"Electrical and Computer Engineering Department, University of Pittsburgh, Pittsburgh, PA, USA","institution_ids":["https://openalex.org/I170201317"]},{"raw_affiliation_string":"Electr. & Comput. Eng. Dept., Univ. of Pittsburgh, PA, USA","institution_ids":["https://openalex.org/I170201317"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5070703425","display_name":"Ivan S. Kourtev","orcid":null},"institutions":[{"id":"https://openalex.org/I170201317","display_name":"University of Pittsburgh","ror":"https://ror.org/01an3r305","country_code":"US","type":"education","lineage":["https://openalex.org/I170201317"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"I.S. Kourtev","raw_affiliation_strings":["Electrical and Computer Engineering Department, University of Pittsburgh, Pittsburgh, PA, USA","Electr. & Comput. Eng. Dept., Univ. of Pittsburgh, PA, USA"],"affiliations":[{"raw_affiliation_string":"Electrical and Computer Engineering Department, University of Pittsburgh, Pittsburgh, PA, USA","institution_ids":["https://openalex.org/I170201317"]},{"raw_affiliation_string":"Electr. & Comput. Eng. Dept., Univ. of Pittsburgh, PA, USA","institution_ids":["https://openalex.org/I170201317"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5081080799"],"corresponding_institution_ids":["https://openalex.org/I170201317"],"apc_list":null,"apc_paid":null,"fwci":0.3557,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.66534449,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"cad 15","issue":null,"first_page":"603","last_page":"606"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9983000159263611,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9907000064849854,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/clock-skew","display_name":"Clock skew","score":0.8417757749557495},{"id":"https://openalex.org/keywords/digital-clock-manager","display_name":"Digital clock manager","score":0.7593913078308105},{"id":"https://openalex.org/keywords/static-timing-analysis","display_name":"Static timing analysis","score":0.7356729507446289},{"id":"https://openalex.org/keywords/timing-failure","display_name":"Timing failure","score":0.7106841802597046},{"id":"https://openalex.org/keywords/skew","display_name":"Skew","score":0.6716705560684204},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.6426136493682861},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6371059417724609},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.555601954460144},{"id":"https://openalex.org/keywords/scheduling","display_name":"Scheduling (production processes)","score":0.5220053791999817},{"id":"https://openalex.org/keywords/clock-gating","display_name":"Clock gating","score":0.5162405967712402},{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.5131124258041382},{"id":"https://openalex.org/keywords/clock-network","display_name":"Clock network","score":0.4640570878982544},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4439780116081238},{"id":"https://openalex.org/keywords/application-specific-integrated-circuit","display_name":"Application-specific integrated circuit","score":0.42277413606643677},{"id":"https://openalex.org/keywords/clock-domain-crossing","display_name":"Clock domain crossing","score":0.4159882962703705},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.39963704347610474},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.30471450090408325},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.18052050471305847},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.17681646347045898},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.1426199972629547},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.1188916265964508},{"id":"https://openalex.org/keywords/mathematical-optimization","display_name":"Mathematical optimization","score":0.08611014485359192},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.06494617462158203}],"concepts":[{"id":"https://openalex.org/C60501442","wikidata":"https://www.wikidata.org/wiki/Q4382014","display_name":"Clock skew","level":4,"score":0.8417757749557495},{"id":"https://openalex.org/C113074038","wikidata":"https://www.wikidata.org/wiki/Q5276052","display_name":"Digital clock manager","level":5,"score":0.7593913078308105},{"id":"https://openalex.org/C93682380","wikidata":"https://www.wikidata.org/wiki/Q2025226","display_name":"Static timing analysis","level":2,"score":0.7356729507446289},{"id":"https://openalex.org/C104654189","wikidata":"https://www.wikidata.org/wiki/Q7806740","display_name":"Timing failure","level":5,"score":0.7106841802597046},{"id":"https://openalex.org/C43711488","wikidata":"https://www.wikidata.org/wiki/Q7534783","display_name":"Skew","level":2,"score":0.6716705560684204},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.6426136493682861},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6371059417724609},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.555601954460144},{"id":"https://openalex.org/C206729178","wikidata":"https://www.wikidata.org/wiki/Q2271896","display_name":"Scheduling (production processes)","level":2,"score":0.5220053791999817},{"id":"https://openalex.org/C22716491","wikidata":"https://www.wikidata.org/wiki/Q590170","display_name":"Clock gating","level":5,"score":0.5162405967712402},{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.5131124258041382},{"id":"https://openalex.org/C2778182565","wikidata":"https://www.wikidata.org/wiki/Q1752879","display_name":"Clock network","level":5,"score":0.4640570878982544},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4439780116081238},{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.42277413606643677},{"id":"https://openalex.org/C127204226","wikidata":"https://www.wikidata.org/wiki/Q5134799","display_name":"Clock domain crossing","level":5,"score":0.4159882962703705},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.39963704347610474},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.30471450090408325},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.18052050471305847},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.17681646347045898},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.1426199972629547},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.1188916265964508},{"id":"https://openalex.org/C126255220","wikidata":"https://www.wikidata.org/wiki/Q141495","display_name":"Mathematical optimization","level":1,"score":0.08611014485359192},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.06494617462158203},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/icecs.2004.1399753","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecs.2004.1399753","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2004 11th IEEE International Conference on Electronics, Circuits and Systems, 2004. ICECS 2004.","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W1875554762","https://openalex.org/W2084481616","https://openalex.org/W2097181398","https://openalex.org/W2099989103","https://openalex.org/W2112242460","https://openalex.org/W2145967198","https://openalex.org/W2155474020","https://openalex.org/W2156162117","https://openalex.org/W4238424602","https://openalex.org/W6674794837"],"related_works":["https://openalex.org/W2088914741","https://openalex.org/W4247180033","https://openalex.org/W2559451387","https://openalex.org/W2144282137","https://openalex.org/W2127892766","https://openalex.org/W3006003651","https://openalex.org/W2617666058","https://openalex.org/W2090213929","https://openalex.org/W2165139624","https://openalex.org/W2384600254"],"abstract_inverted_index":{"The":[0,30,81],"paper":[1],"addresses":[2],"the":[3,64,72,94,97,107,129,149],"advanced":[4],"timing":[5,31,65],"analysis":[6,32,66],"of":[7,77,86,96,132,142],"multiphase":[8,59,78,155],"level-sensitive":[9,79,113],"synchronous":[10],"circuits":[11,125],"under":[12,153],"clock":[13,73,98,122,134],"skew":[14,135],"scheduling":[15,136],"(Kourtev,":[16],"I.S.":[17],"and":[18,43,88,102,137],"Friedman,":[19],"E.G.,":[20],"\"Optimization":[21],"Through":[22],"Clock":[23],"Skew":[24],"Scheduling\",":[25],"Kluwer":[26],"Academic":[27],"Publishers,":[28],"2000).":[29],"framework":[33,67],"previously":[34],"offered":[35],"for":[36,148],"a":[37,58,154],"single-phase":[38,112],"clocking":[39,60,156],"scheme":[40],"(Taskin,":[41],"B.":[42],"Kourtev,":[44],"I.S.,":[45],"Proc.":[46],"15th":[47],"IEEE":[48],"Int.":[49],"ASIC/SOC":[50],"Conf.":[51],"p.358-62,":[52],"2002)":[53],"is":[54,68,90],"enhanced":[55],"to":[56,70,92,116,144],"accommodate":[57],"scheme.":[61,157],"In":[62,111],"particular,":[63],"used":[69,91],"formulate":[71],"period":[74,99],"minimization":[75,100],"problem":[76,101],"circuits.":[80,110],"modified":[82],"big":[83],"M":[84],"method":[85],"Taskin":[87],"Kourtev":[89],"linearize":[93],"formulation":[95],"experiments":[103],"are":[104,126,146],"performed":[105],"on":[106],"ISCAS'89":[108],"benchmark":[109],"circuits,":[114],"up":[115,143],"63%":[117],"improvements":[118,141],"over":[119],"conventional":[120],"zero":[121],"skew,":[123],"edge-triggered":[124],"achieved":[127,147],"through":[128],"simultaneous":[130],"application":[131],"non-zero":[133],"time":[138],"borrowing.":[139],"Comparable":[140],"62%":[145],"same":[150],"circuit":[151],"topologies":[152]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
