{"id":"https://openalex.org/W2541906669","doi":"https://doi.org/10.1109/icecs.2004.1399750","title":"Investigation of on-chip PLL irregularities under stress conditions - case study","display_name":"Investigation of on-chip PLL irregularities under stress conditions - case study","publication_year":2005,"publication_date":"2005-03-31","ids":{"openalex":"https://openalex.org/W2541906669","doi":"https://doi.org/10.1109/icecs.2004.1399750","mag":"2541906669"},"language":"en","primary_location":{"id":"doi:10.1109/icecs.2004.1399750","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecs.2004.1399750","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2004 11th IEEE International Conference on Electronics, Circuits and Systems, 2004. ICECS 2004.","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5057416540","display_name":"Yoav Weizman","orcid":null},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"Y. Weizman","raw_affiliation_strings":["Freescale Semiconductor Israel Limited, Herzliya, Israel"],"affiliations":[{"raw_affiliation_string":"Freescale Semiconductor Israel Limited, Herzliya, Israel","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5031087443","display_name":"Y. Fefer","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Y. Fefer","raw_affiliation_strings":["Freescale Semiconductor Israel Limited, Herzliya, Israel"],"affiliations":[{"raw_affiliation_string":"Freescale Semiconductor Israel Limited, Herzliya, Israel","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5033919783","display_name":"Sergey Sofer","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"S. Sofer","raw_affiliation_strings":["Freescale Semiconductor Israel Limited, Herzliya, Israel"],"affiliations":[{"raw_affiliation_string":"Freescale Semiconductor Israel Limited, Herzliya, Israel","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5021358424","display_name":"E. Baruch","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"E. Baruch","raw_affiliation_strings":["Freescale Semiconductor Israel Limited, Herzliya, Israel"],"affiliations":[{"raw_affiliation_string":"Freescale Semiconductor Israel Limited, Herzliya, Israel","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5057416540"],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.7114,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.76393369,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"591","last_page":"594"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11444","display_name":"Electromagnetic Compatibility and Noise Suppression","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"Phase-locked loop","score":0.9486157894134521},{"id":"https://openalex.org/keywords/pll-multibit","display_name":"PLL multibit","score":0.7912704944610596},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5907893180847168},{"id":"https://openalex.org/keywords/phase-noise","display_name":"Phase noise","score":0.49395591020584106},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.4698459506034851},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.41445767879486084},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.4141656160354614},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.40849244594573975},{"id":"https://openalex.org/keywords/control-theory","display_name":"Control theory (sociology)","score":0.3702958822250366},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.25744664669036865}],"concepts":[{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.9486157894134521},{"id":"https://openalex.org/C77881186","wikidata":"https://www.wikidata.org/wiki/Q7119642","display_name":"PLL multibit","level":4,"score":0.7912704944610596},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5907893180847168},{"id":"https://openalex.org/C89631360","wikidata":"https://www.wikidata.org/wiki/Q1428766","display_name":"Phase noise","level":2,"score":0.49395591020584106},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.4698459506034851},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.41445767879486084},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.4141656160354614},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.40849244594573975},{"id":"https://openalex.org/C47446073","wikidata":"https://www.wikidata.org/wiki/Q5165890","display_name":"Control theory (sociology)","level":3,"score":0.3702958822250366},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.25744664669036865},{"id":"https://openalex.org/C2775924081","wikidata":"https://www.wikidata.org/wiki/Q55608371","display_name":"Control (management)","level":2,"score":0.0},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/icecs.2004.1399750","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecs.2004.1399750","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2004 11th IEEE International Conference on Electronics, Circuits and Systems, 2004. ICECS 2004.","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":6,"referenced_works":["https://openalex.org/W1580873078","https://openalex.org/W2104415993","https://openalex.org/W2163854931","https://openalex.org/W2180333551","https://openalex.org/W2490904451","https://openalex.org/W2541867884"],"related_works":["https://openalex.org/W1576949837","https://openalex.org/W984417604","https://openalex.org/W2498262093","https://openalex.org/W2474043983","https://openalex.org/W2544336511","https://openalex.org/W2566880546","https://openalex.org/W2078513307","https://openalex.org/W1978186604","https://openalex.org/W2144737022","https://openalex.org/W2124954209"],"abstract_inverted_index":{"In":[0],"modern":[1],"high":[2],"performance":[3,11],"VLSI":[4],"design,":[5],"on-chip":[6],"phase":[7],"locked":[8],"loop":[9],"(PLL)":[10],"degradation":[12],"due":[13],"to":[14,98],"intensive":[15,48],"core":[16,49,75],"switching":[17],"activities":[18],"is":[19],"becoming":[20],"an":[21],"influential":[22],"factor.":[23],"Under":[24],"certain":[25],"borderline":[26],"conditions,":[27,132],"the":[28,62,80,85,90,93,99,105,114,127,135],"PLL":[29,37,91,106,128,138],"may":[30],"become":[31],"unstable.":[32],"The":[33,96],"analysis":[34,53,139],"herein":[35],"describes":[36],"irregularities":[38],"under":[39,130],"marginal":[40],"mode,":[41],"frequency":[42],"and":[43,79,122,125],"voltage":[44,72,86],"conditions":[45],"combined":[46],"with":[47],"operations.":[50],"After":[51],"lengthy":[52],"that":[54],"included":[55],"step-by-step":[56],"elimination":[57],"of":[58,64,84,89,137],"all":[59],"noise":[60,115],"sources,":[61],"cause":[63],"instability":[65],"was":[66,101],"explained":[67],"by":[68,103],"coupling":[69],"between":[70],"a":[71,141],"spike":[73],"on":[74],"power":[76],"supply":[77],"line":[78],"internal":[81],"control":[82],"signal":[83],"controlled":[87],"oscillator":[88],"through":[92],"chip":[94],"substrate.":[95],"solution":[97],"problem":[100],"suggested":[102],"changing":[104],"dynamic":[107],"characteristics.":[108],"Through":[109],"this":[110],"investigation":[111],"we":[112],"studied":[113],"crosstalk":[116],"issue":[117],"in":[118,140],"mixed":[119],"mode":[120],"(analog":[121],"digital)":[123],"systems":[124],"also":[126],"dynamics":[129],"stress":[131],"which":[133],"demonstrates":[134],"complexity":[136],"system-on-chip":[142],"environment.":[143]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}