{"id":"https://openalex.org/W2164354632","doi":"https://doi.org/10.1109/icecs.2004.1399729","title":"SystemC opportunities in chip design flow","display_name":"SystemC opportunities in chip design flow","publication_year":2005,"publication_date":"2005-03-31","ids":{"openalex":"https://openalex.org/W2164354632","doi":"https://doi.org/10.1109/icecs.2004.1399729","mag":"2164354632"},"language":"en","primary_location":{"id":"doi:10.1109/icecs.2004.1399729","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecs.2004.1399729","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2004 11th IEEE International Conference on Electronics, Circuits and Systems, 2004. ICECS 2004.","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5083700985","display_name":"Itai Yarom","orcid":null},"institutions":[{"id":"https://openalex.org/I4210104622","display_name":"Intel (Israel)","ror":"https://ror.org/027t2s119","country_code":"IL","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210104622"]}],"countries":["IL"],"is_corresponding":true,"raw_author_name":"I. Yarom","raw_affiliation_strings":["LAN Access Division, Intel Design Center, Jerusalem, Israel"],"affiliations":[{"raw_affiliation_string":"LAN Access Division, Intel Design Center, Jerusalem, Israel","institution_ids":["https://openalex.org/I4210104622"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5015323248","display_name":"G. Glasser","orcid":null},"institutions":[{"id":"https://openalex.org/I4210104622","display_name":"Intel (Israel)","ror":"https://ror.org/027t2s119","country_code":"IL","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210104622"]}],"countries":["IL"],"is_corresponding":false,"raw_author_name":"G. Glasser","raw_affiliation_strings":["LAN Access Division, Intel Design Center, Jerusalem, Israel"],"affiliations":[{"raw_affiliation_string":"LAN Access Division, Intel Design Center, Jerusalem, Israel","institution_ids":["https://openalex.org/I4210104622"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5083700985"],"corresponding_institution_ids":["https://openalex.org/I4210104622"],"apc_list":null,"apc_paid":null,"fwci":1.5469,"has_fulltext":false,"cited_by_count":8,"citation_normalized_percentile":{"value":0.84470663,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"q4","issue":null,"first_page":"507","last_page":"510"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9970999956130981,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9944999814033508,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/systemc","display_name":"SystemC","score":0.987571656703949},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.7179975509643555},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6779553890228271},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.574774980545044},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.5723448991775513},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.5174242258071899},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4984397888183594},{"id":"https://openalex.org/keywords/integrated-circuit-design","display_name":"Integrated circuit design","score":0.4665379822254181},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.4161127209663391},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.11071309447288513}],"concepts":[{"id":"https://openalex.org/C2776928060","wikidata":"https://www.wikidata.org/wiki/Q1753563","display_name":"SystemC","level":2,"score":0.987571656703949},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.7179975509643555},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6779553890228271},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.574774980545044},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.5723448991775513},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.5174242258071899},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4984397888183594},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.4665379822254181},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.4161127209663391},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.11071309447288513},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/icecs.2004.1399729","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecs.2004.1399729","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2004 11th IEEE International Conference on Electronics, Circuits and Systems, 2004. ICECS 2004.","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":2,"referenced_works":["https://openalex.org/W79022431","https://openalex.org/W6603205614"],"related_works":["https://openalex.org/W2379408401","https://openalex.org/W3047418593","https://openalex.org/W1996778651","https://openalex.org/W47369351","https://openalex.org/W1603163876","https://openalex.org/W3151664512","https://openalex.org/W2102117846","https://openalex.org/W2533063779","https://openalex.org/W4230718388","https://openalex.org/W2047284788"],"abstract_inverted_index":{"Moore's":[0],"law":[1],"predicts":[2],"that":[3],"the":[4,23,27,35,43,59,93],"number":[5],"of":[6,22,45,71,79,101],"transistors":[7],"in":[8,17,34,48,58,81,92],"a":[9,99],"system":[10,89],"will":[11],"double":[12],"every":[13],"18":[14],"months.":[15],"However,":[16],"order":[18,49],"to":[19,31,50,103],"take":[20],"advantage":[21],"chip":[24,36],"technology":[25,47],"progress,":[26],"same":[28],"progress":[29],"needs":[30],"be":[32],"made":[33],"design":[37,82,94],"process.":[38],"The":[39,74],"paper":[40],"focuses":[41],"on":[42],"benefit":[44],"SystemC":[46,80,102],"close":[51],"this":[52],"gap.":[53],"We":[54],"present":[55],"research":[56,75],"done":[57],"Intel":[60],"Development":[61],"Center":[62],"(IDC)":[63],"with":[64],"Tel-Aviv":[65],"University":[66],"(TAU)":[67],"and":[68,83,98],"Jerusalem":[69],"College":[70],"Technology":[72],"(JCT).":[73],"explores":[76],"different":[77],"usages":[78],"verification":[84,90],"flow,":[85],"which":[86],"includes":[87],"soft":[88],"(early":[91],"flows),":[95],"architecture":[96],"tradeoffs":[97],"flow":[100],"gate-level":[104],"flow.":[105]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}