{"id":"https://openalex.org/W2105915284","doi":"https://doi.org/10.1109/icecs.2004.1399705","title":"Optimal resizing of bus wires in layout migration","display_name":"Optimal resizing of bus wires in layout migration","publication_year":2005,"publication_date":"2005-03-31","ids":{"openalex":"https://openalex.org/W2105915284","doi":"https://doi.org/10.1109/icecs.2004.1399705","mag":"2105915284"},"language":"en","primary_location":{"id":"doi:10.1109/icecs.2004.1399705","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecs.2004.1399705","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2004 11th IEEE International Conference on Electronics, Circuits and Systems, 2004. ICECS 2004.","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5019167884","display_name":"S. Michaely","orcid":null},"institutions":[{"id":"https://openalex.org/I174306211","display_name":"Technion \u2013 Israel Institute of Technology","ror":"https://ror.org/03qryx823","country_code":"IL","type":"education","lineage":["https://openalex.org/I174306211"]}],"countries":["IL"],"is_corresponding":true,"raw_author_name":"S. Michaely","raw_affiliation_strings":["Electrical Engineering Department, Technion-Israel Institute of Technology, Haifa, Israel"],"affiliations":[{"raw_affiliation_string":"Electrical Engineering Department, Technion-Israel Institute of Technology, Haifa, Israel","institution_ids":["https://openalex.org/I174306211"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5000817401","display_name":"Shmuel Wimer","orcid":"https://orcid.org/0000-0002-5728-0061"},"institutions":[{"id":"https://openalex.org/I4210104622","display_name":"Intel (Israel)","ror":"https://ror.org/027t2s119","country_code":"IL","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210104622"]},{"id":"https://openalex.org/I80687555","display_name":"Israel Electric (Israel)","ror":"https://ror.org/01p8dnv11","country_code":"IL","type":"company","lineage":["https://openalex.org/I80687555"]}],"countries":["IL"],"is_corresponding":false,"raw_author_name":"S. Wimer","raw_affiliation_strings":["Mobile Processor Group, Intel Corporation, Haifa, Israel"],"affiliations":[{"raw_affiliation_string":"Mobile Processor Group, Intel Corporation, Haifa, Israel","institution_ids":["https://openalex.org/I80687555","https://openalex.org/I4210104622"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5051888366","display_name":"Avinoam Kolodny","orcid":null},"institutions":[{"id":"https://openalex.org/I174306211","display_name":"Technion \u2013 Israel Institute of Technology","ror":"https://ror.org/03qryx823","country_code":"IL","type":"education","lineage":["https://openalex.org/I174306211"]}],"countries":["IL"],"is_corresponding":false,"raw_author_name":"A. Kolodny","raw_affiliation_strings":["Electrical Engineering Department, Technion-Israel Institute of Technology, Haifa, Israel"],"affiliations":[{"raw_affiliation_string":"Electrical Engineering Department, Technion-Israel Institute of Technology, Haifa, Israel","institution_ids":["https://openalex.org/I174306211"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5019167884"],"corresponding_institution_ids":["https://openalex.org/I174306211"],"apc_list":null,"apc_paid":null,"fwci":1.0883,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.79864646,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"411","last_page":"414"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/constraint","display_name":"Constraint (computer-aided design)","score":0.6116098761558533},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5537968277931213},{"id":"https://openalex.org/keywords/scaling","display_name":"Scaling","score":0.5404622554779053},{"id":"https://openalex.org/keywords/resizing","display_name":"Resizing","score":0.5239225029945374},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4650847315788269},{"id":"https://openalex.org/keywords/optimal-design","display_name":"Optimal design","score":0.44078707695007324},{"id":"https://openalex.org/keywords/signal","display_name":"SIGNAL (programming language)","score":0.431968629360199},{"id":"https://openalex.org/keywords/integrated-circuit-layout","display_name":"Integrated circuit layout","score":0.42482417821884155},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.29952582716941833},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2739139795303345},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.1829146444797516},{"id":"https://openalex.org/keywords/mechanical-engineering","display_name":"Mechanical engineering","score":0.12530875205993652},{"id":"https://openalex.org/keywords/geometry","display_name":"Geometry","score":0.09214907884597778}],"concepts":[{"id":"https://openalex.org/C2776036281","wikidata":"https://www.wikidata.org/wiki/Q48769818","display_name":"Constraint (computer-aided design)","level":2,"score":0.6116098761558533},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5537968277931213},{"id":"https://openalex.org/C99844830","wikidata":"https://www.wikidata.org/wiki/Q102441924","display_name":"Scaling","level":2,"score":0.5404622554779053},{"id":"https://openalex.org/C56281022","wikidata":"https://www.wikidata.org/wiki/Q11308039","display_name":"Resizing","level":3,"score":0.5239225029945374},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4650847315788269},{"id":"https://openalex.org/C186394612","wikidata":"https://www.wikidata.org/wiki/Q7098942","display_name":"Optimal design","level":2,"score":0.44078707695007324},{"id":"https://openalex.org/C2779843651","wikidata":"https://www.wikidata.org/wiki/Q7390335","display_name":"SIGNAL (programming language)","level":2,"score":0.431968629360199},{"id":"https://openalex.org/C2765594","wikidata":"https://www.wikidata.org/wiki/Q2624187","display_name":"Integrated circuit layout","level":3,"score":0.42482417821884155},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.29952582716941833},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2739139795303345},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.1829146444797516},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.12530875205993652},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.09214907884597778},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C144133560","wikidata":"https://www.wikidata.org/wiki/Q4830453","display_name":"Business","level":0,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C2910001868","wikidata":"https://www.wikidata.org/wiki/Q458","display_name":"European union","level":2,"score":0.0},{"id":"https://openalex.org/C105639569","wikidata":"https://www.wikidata.org/wiki/Q582577","display_name":"Economic policy","level":1,"score":0.0},{"id":"https://openalex.org/C119857082","wikidata":"https://www.wikidata.org/wiki/Q2539","display_name":"Machine learning","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/icecs.2004.1399705","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecs.2004.1399705","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2004 11th IEEE International Conference on Electronics, Circuits and Systems, 2004. ICECS 2004.","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.128.2025","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.128.2025","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.ee.technion.ac.il/people/kolodny/ftp/01399705buswireresizing.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":17,"referenced_works":["https://openalex.org/W2014919362","https://openalex.org/W2098414078","https://openalex.org/W2110811521","https://openalex.org/W2113222277","https://openalex.org/W2113537658","https://openalex.org/W2121424172","https://openalex.org/W2121626067","https://openalex.org/W2165210723","https://openalex.org/W2169531002","https://openalex.org/W2171410364","https://openalex.org/W2171825402","https://openalex.org/W4229741927","https://openalex.org/W4231387309","https://openalex.org/W4233101964","https://openalex.org/W6677706691","https://openalex.org/W6678018155","https://openalex.org/W6684514280"],"related_works":["https://openalex.org/W246416693","https://openalex.org/W647263804","https://openalex.org/W4200241426","https://openalex.org/W163671557","https://openalex.org/W1579571183","https://openalex.org/W4390595827","https://openalex.org/W2166847561","https://openalex.org/W2187212653","https://openalex.org/W2743403117","https://openalex.org/W2364276563"],"abstract_inverted_index":{"The":[0],"effect":[1],"of":[2,20,39,55,67,88],"wire":[3,24,81],"delay":[4],"on":[5],"circuit":[6],"timing":[7,37],"typically":[8],"increases":[9],"when":[10],"an":[11,74],"existing":[12],"layout":[13],"is":[14,42,60,85],"migrated":[15],"to":[16,77],"a":[17,63],"new":[18],"generation":[19],"processing":[21],"technology,":[22],"because":[23],"resistance":[25],"and":[26,46,73,83],"cross":[27],"capacitances":[28],"become":[29],"more":[30],"important":[31],"with":[32],"scaling.":[33],"In":[34],"this":[35],"paper,":[36],"optimization":[38],"signal":[40],"buses":[41],"performed":[43],"by":[44],"resizing":[45],"spacing":[47],"individual":[48],"bus":[49,58,69],"wires,":[50],"while":[51],"the":[52,56,79],"total":[53],"area":[54],"whole":[57],"structure":[59],"regarded":[61],"as":[62],"fixed":[64],"constraint.":[65],"Properties":[66],"optimal":[68,80],"layouts":[70],"are":[71,90,95],"proven,":[72],"iterative":[75],"algorithm":[76],"find":[78],"widths":[82],"spaces":[84],"presented.":[86],"Examples":[87],"solutions":[89],"shown.":[91],"Guidelines":[92],"for":[93],"design":[94],"derived":[96],"from":[97],"these":[98],"results.":[99]},"counts_by_year":[],"updated_date":"2026-04-04T16:13:02.066488","created_date":"2025-10-10T00:00:00"}
