{"id":"https://openalex.org/W2540972939","doi":"https://doi.org/10.1109/icecs.2004.1399643","title":"A 0.8V CMOS TSPC adiabatic DCVS logic circuit with the bootstrap technique for low-power VLSI","display_name":"A 0.8V CMOS TSPC adiabatic DCVS logic circuit with the bootstrap technique for low-power VLSI","publication_year":2005,"publication_date":"2005-03-31","ids":{"openalex":"https://openalex.org/W2540972939","doi":"https://doi.org/10.1109/icecs.2004.1399643","mag":"2540972939"},"language":"en","primary_location":{"id":"doi:10.1109/icecs.2004.1399643","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecs.2004.1399643","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2004 11th IEEE International Conference on Electronics, Circuits and Systems, 2004. ICECS 2004.","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5067641804","display_name":"H.P. Chen","orcid":null},"institutions":[{"id":"https://openalex.org/I16733864","display_name":"National Taiwan University","ror":"https://ror.org/05bqach95","country_code":"TW","type":"education","lineage":["https://openalex.org/I16733864"]}],"countries":["TW"],"is_corresponding":true,"raw_author_name":"H.P. Chen","raw_affiliation_strings":["Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan","institution_ids":["https://openalex.org/I16733864"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5024957250","display_name":"J.B. Kuo","orcid":"https://orcid.org/0000-0003-1391-1586"},"institutions":[{"id":"https://openalex.org/I16733864","display_name":"National Taiwan University","ror":"https://ror.org/05bqach95","country_code":"TW","type":"education","lineage":["https://openalex.org/I16733864"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"J.B. Kuo","raw_affiliation_strings":["Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan","institution_ids":["https://openalex.org/I16733864"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5067641804"],"corresponding_institution_ids":["https://openalex.org/I16733864"],"apc_list":null,"apc_paid":null,"fwci":2.1772,"has_fulltext":false,"cited_by_count":9,"citation_normalized_percentile":{"value":0.8857805,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":"33","issue":null,"first_page":"175","last_page":"178"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/adiabatic-circuit","display_name":"Adiabatic circuit","score":0.9122251272201538},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.7008156180381775},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.6675960421562195},{"id":"https://openalex.org/keywords/pass-transistor-logic","display_name":"Pass transistor logic","score":0.6248378157615662},{"id":"https://openalex.org/keywords/pmos-logic","display_name":"PMOS logic","score":0.5708460807800293},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.5236151814460754},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.5090572237968445},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.5008811950683594},{"id":"https://openalex.org/keywords/cascode","display_name":"Cascode","score":0.4913610517978668},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4765228033065796},{"id":"https://openalex.org/keywords/adiabatic-process","display_name":"Adiabatic process","score":0.4566648602485657},{"id":"https://openalex.org/keywords/integrated-injection-logic","display_name":"Integrated injection logic","score":0.45113760232925415},{"id":"https://openalex.org/keywords/capacitance","display_name":"Capacitance","score":0.4353744387626648},{"id":"https://openalex.org/keywords/emitter-coupled-logic","display_name":"Emitter-coupled logic","score":0.41893717646598816},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.3962910771369934},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.36653614044189453},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.35609060525894165},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.3255664110183716},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.2640589475631714},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.21035048365592957},{"id":"https://openalex.org/keywords/electrode","display_name":"Electrode","score":0.056184858083724976}],"concepts":[{"id":"https://openalex.org/C87606752","wikidata":"https://www.wikidata.org/wiki/Q4682637","display_name":"Adiabatic circuit","level":5,"score":0.9122251272201538},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.7008156180381775},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.6675960421562195},{"id":"https://openalex.org/C198521697","wikidata":"https://www.wikidata.org/wiki/Q7142438","display_name":"Pass transistor logic","level":4,"score":0.6248378157615662},{"id":"https://openalex.org/C27050352","wikidata":"https://www.wikidata.org/wiki/Q173605","display_name":"PMOS logic","level":4,"score":0.5708460807800293},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.5236151814460754},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.5090572237968445},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.5008811950683594},{"id":"https://openalex.org/C2775946640","wikidata":"https://www.wikidata.org/wiki/Q1735017","display_name":"Cascode","level":4,"score":0.4913610517978668},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4765228033065796},{"id":"https://openalex.org/C109663097","wikidata":"https://www.wikidata.org/wiki/Q182453","display_name":"Adiabatic process","level":2,"score":0.4566648602485657},{"id":"https://openalex.org/C159903706","wikidata":"https://www.wikidata.org/wiki/Q173574","display_name":"Integrated injection logic","level":5,"score":0.45113760232925415},{"id":"https://openalex.org/C30066665","wikidata":"https://www.wikidata.org/wiki/Q164399","display_name":"Capacitance","level":3,"score":0.4353744387626648},{"id":"https://openalex.org/C11644886","wikidata":"https://www.wikidata.org/wiki/Q173552","display_name":"Emitter-coupled logic","level":5,"score":0.41893717646598816},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.3962910771369934},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.36653614044189453},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.35609060525894165},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.3255664110183716},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.2640589475631714},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.21035048365592957},{"id":"https://openalex.org/C17525397","wikidata":"https://www.wikidata.org/wiki/Q176140","display_name":"Electrode","level":2,"score":0.056184858083724976},{"id":"https://openalex.org/C97355855","wikidata":"https://www.wikidata.org/wiki/Q11473","display_name":"Thermodynamics","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1109/icecs.2004.1399643","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecs.2004.1399643","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2004 11th IEEE International Conference on Electronics, Circuits and Systems, 2004. ICECS 2004.","raw_type":"proceedings-article"},{"id":"pmh:oai:140.112.114.62:246246/200704191001664","is_oa":false,"landing_page_url":"http://ntur.lib.ntu.edu.tw//handle/246246/200704191001664","pdf_url":null,"source":{"id":"https://openalex.org/S4306402491","display_name":"NTUR (\u81fa\u7063\u6a5f\u69cb\u5178\u85cf)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I16733864","host_organization_name":"National Taiwan University","host_organization_lineage":["https://openalex.org/I16733864"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.391.9275","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.391.9275","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://ntur.lib.ntu.edu.tw/bitstream/246246/200704191001664/1/01399643.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.8899999856948853,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[{"id":"https://openalex.org/G7863819610","display_name":null,"funder_award_id":"R.O.C","funder_id":"https://openalex.org/F4320321040","funder_display_name":"National Science Council"}],"funders":[{"id":"https://openalex.org/F4320321040","display_name":"National Science Council","ror":"https://ror.org/02kv4zf79"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W398027425","https://openalex.org/W2033609308","https://openalex.org/W2059568891","https://openalex.org/W2066134400","https://openalex.org/W2120187194","https://openalex.org/W2123607016","https://openalex.org/W2169721199"],"related_works":["https://openalex.org/W2965791759","https://openalex.org/W2017528947","https://openalex.org/W2765372174","https://openalex.org/W2894573466","https://openalex.org/W1485027372","https://openalex.org/W2580743037","https://openalex.org/W2169842719","https://openalex.org/W2108907112","https://openalex.org/W2554253794","https://openalex.org/W2539423522"],"abstract_inverted_index":{"The":[0],"paper":[1],"reports":[2],"a":[3],"novel":[4],"0.8":[5,50],"V":[6,51],"CMOS":[7],"true-single-phase-clocking":[8],"(TSPC)":[9],"adiabatic":[10,53,73],"differential":[11],"cascode":[12],"voltage":[13],"switch":[14],"(DCVS)":[15],"logic":[16,55],"circuit":[17,56],"with":[18,57],"the":[19,26,32,42,46,58,68,71],"bootstrap":[20,47,59],"technique":[21,60],"for":[22,38],"low-power":[23],"VLSI.":[24],"Via":[25],"pass":[27],"transistors":[28],"and":[29],"compensating":[30],"transistors,":[31,48],"TSPC":[33,52],"scheme":[34],"has":[35],"been":[36],"obtained":[37],"easy":[39],"clocking.":[40],"Using":[41],"capacitance":[43],"coupling":[44],"from":[45],"this":[49],"DCVS":[54],"consumes":[61],"31%":[62],"less":[63],"energy":[64],"as":[65],"compared":[66],"to":[67],"one":[69],"using":[70],"clocked":[72],"latch":[74],"(CAL)":[75],"approach.":[76]},"counts_by_year":[{"year":2012,"cited_by_count":1}],"updated_date":"2026-04-10T15:06:20.359241","created_date":"2025-10-10T00:00:00"}